As processor clock frequencies continue to improve at a rate that exceeds the rate of improvement in the performance of semiconductor memories, so the effect of memory latency on processor efficiency increases. Unless steps are taken to mitigate the effect of memory latency, the increased processor frequency is of little benefit. This work demonstrates how multithreading can reduce the effect of memory latency on processor performance and how just a few threads are required to achieve close to optimal performance. A lightweight multithreaded architecture is discussed and simulated to show how threads derived from an application's instruction-level parallelism may be used to tolerate memory latency.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:248066 |
| Date | January 2002 |
| Creators | Gale, Andrew |
| Publisher | University of Surrey |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://epubs.surrey.ac.uk/842940/ |
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