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Networks-on-chip for multiprocessors

It is anticipated that with further transistor dimension scaling as well as packaging innovation, the transistor budget will keep increasing in the next decade. However, as the benefits of transistor scaling decrease, little performance improvement and reduction in switching energy can be archived by the scaling. Bounded by slow memory and increased power, the performance of microprocessor reaches the point of diminishing return. The main focus of this thesis is to develop an effective on-chip communication architecture and processor architecture for next generation multiprocessor on a single hard wired silicon chip, or a programmable chip such as FPGA, allowing the physical property and performance of the architecture to scale with the ever increasing transistor budget offered by new technology node. A Networks-on-Chip (NoC) centric system design has been presented. This explores the main attraction of the scalability of NoC, which contrasts traditional multiprocessor interconnects, such as shared bus and crossbar, which are not scalable in terms of their performance and cost. In addition, a novel multithreading processor architecture has been developed with fast with fast single cycle thread scheduling that is capable of allocating the computation resources to the threads doing computational work rather than the threads waiting for data communication.
Date January 2012
CreatorsLu, Ye
PublisherQueen's University Belfast
Source SetsEthos UK
Detected LanguageEnglish
TypeElectronic Thesis or Dissertation

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