Future memory subsystems will have to achieve high performance, low power, high reliability, small size and high robustness under process variation. Moreover, it should be possible to build them with reasonable yield. Thus, design methodologies are needed to enhance the behaviors and yield of these systems. Increasing process variation effects on the design metrics also need to be evaluated, such as performance and power consumption. This dissertation addresses these problems. First, it proposes a novel SRAM bitcell design based on a promising technology, carbon nanotube field-effect-transistor (CNTFET). This CNTFET-based SRAM design offers better stability, lower power dissipation and better process variation tolerant ability, compared with CMOS-based and other CNTFET-based SRAM bitcells. However, carbon nanotubes (CNTs) can be either semi-conductive or metallic during fabrication so that CNTFETs suffer from short circuit unreliability due to the metallic path between the source and drain. Therefore, the metallic CNT tolerant techniques are applied to the proposed SRAM design to improve the probabilities of functional SRAM cells. The structure of the CNTFET SRAM design with metallic CNT tolerance is evaluated and compared to the original CNTFET-based SRAM bitcell. The low power binary tree based SRAM architecture (LPSRAM) is then presented. This is a methodology for the future multi-gigabit SRAM designs so that they can obtain high performance, low power and high robustness at the expense of a reasonable area overhead. The analytical models are developed to evaluate the performance, power and the cost of this structure. Empirical simulations are used to verify the proposed LPSRAM analytical models. The results show that the maximum relative model error is within 8%. Moreover, future SRAMs designs need to be easily testable. LPSRAM shows great potential for testability. The testing algorithm and built-in-testing structure (BITS) are developed for the testable LPSRAM architecture. A reduction in testing time and power can be obtained by the proposed architecture. Performance of IC designs is becoming more sensitive to process variation as the technology continues to scale down to nanometer levels. The statistical blockade (SB) approach has recently been proposed to study the impact of process variation and to identify rare events, especially for high-replicated circuits, such as SRAMs. Nevertheless, the threshold of classification and the training sample size are key problems that will cause the imprecise yield estimation and more runtime. Two improved SB algorithms are proposed to address these issues. The experimental results are reported to show that a fast speed can be achieved with high accuracy. A novel variability evaluation approach is then developed based on the enhanced statistical blockade method. Only the tail part of the distribution is used to evaluate the design robustness under process variation, thus, saving time. Four SRAM cells in different logic styles are used to verify the effectiveness of the approach in the experiments. The results show that our method is faster than traditional estimation approaches. In summary, this dissertation reports on the advanced SRAM structures at both circuit level and architectural-level. A fast and accurate method to analyze yield and variability has been presented for the high replicated SRAMs under process variation.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:684909 |
| Date | January 2014 |
| Creators | Sun, Luo |
| Publisher | University of Bristol |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
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