by Yeung Ming Sang. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 191-[201]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Broadband Integrated Services Network --- p.1 / Chapter 1.1.2 --- ATM Switching Technology --- p.3 / Chapter 1.2 --- Broadband ATM Switching ´ؤ A Review --- p.4 / Chapter 1.2.1 --- Shared Memory Switches --- p.5 / Chapter 1.2.2 --- Shared Medium Switches --- p.5 / Chapter 1.2.3 --- Space-division Type Switches --- p.6 / Chapter 1.3 --- Motivation and Contributions --- p.13 / Chapter 1.4 --- Overview of the Thesis --- p.13 / Chapter 2 --- Pipeline Banyan Switch Architecture --- p.15 / Chapter 2.1 --- Switch Architecture --- p.15 / Chapter 2.2 --- Switch Operation --- p.17 / Chapter 2.3 --- Switch Design --- p.19 / Chapter 2.4 --- "Priority, Broadcasting and Multicasting Mechanisms" --- p.21 / Chapter 2.5 --- Switch Speed Reduction at the Control Plane --- p.23 / Chapter 3 --- Performance Evaluation of Pipeline Banyan --- p.27 / Chapter 3.1 --- Performance under Uniform and Independent Traffic Pattern --- p.27 / Chapter 3.1.1 --- Analysis of Packet Loss Performance --- p.27 / Chapter 3.1.2 --- Throughput Performance --- p.32 / Chapter 3.1.3 --- Delay Performance --- p.36 / Chapter 3.1.4 --- Comparison of Loss Performance of Banyan-type Networks --- p.37 / Chapter 3.1.5 --- Output Queueing Capability --- p.41 / Chapter 3.2 --- Performance of the Switch under Special Traffic Pattern --- p.45 / Chapter 3.2.1 --- Performance under Bursty Traffic --- p.45 / Chapter 3.2.2 --- Performance under Hot Spot Traffic --- p.48 / Chapter 3.2.3 --- Performance under Point-to-Point Traffic --- p.51 / Chapter 3.2.4 --- Performance under Permutation Traffic --- p.52 / Chapter 3.3 --- Switch Complexity Discussion --- p.54 / Chapter 4 --- Multi-Channel Pipeline Banyan (MCPB) --- p.57 / Chapter 4.1 --- Background --- p.57 / Chapter 4.2 --- Switch Architecture --- p.59 / Chapter 4.3 --- Performance Evaluation --- p.64 / Chapter 4.3.1 --- Packet loss probability --- p.64 / Chapter 4.3.2 --- Throughput performance --- p.69 / Chapter 4.3.3 --- Delay performance --- p.69 / Chapter 4.4 --- Application of MCPB --- p.71 / Chapter 4.4.1 --- ATM Cross-connect --- p.71 / Chapter 4.4.2 --- Switch Interconnection Fabric --- p.71 / Chapter 5 --- VLSI Implementation --- p.75 / Chapter 5.1 --- Outline of a typical ATM switching system --- p.75 / Chapter 5.1.1 --- Line Interface Module --- p.75 / Chapter 5.1.2 --- System Manager Module --- p.77 / Chapter 5.1.3 --- Switch Module --- p.78 / Chapter 5.2 --- "VLSI Design Technology, Procedures and Tools" --- p.78 / Chapter 5.2.1 --- Design Technology --- p.78 / Chapter 5.2.2 --- Procedures and Tools --- p.79 / Chapter 5.3 --- Logic Design of ATM Switch Module --- p.80 / Chapter 5.3.1 --- Switching Element in Control Plane --- p.80 / Chapter 5.3.2 --- Switching Element in Data Plane --- p.86 / Chapter 5.3.3 --- Clock Generator for Synchronization --- p.93 / Chapter 5.3.4 --- Schematic of Control Plane --- p.98 / Chapter 5.3.5 --- Schematic of Data Plane --- p.98 / Chapter 5.3.6 --- Timing Diagrams --- p.98 / Chapter 5.4 --- Chip Summary --- p.107 / Chapter 5.5 --- Experiences --- p.109 / Chapter 5.5.1 --- Core Size Limitation --- p.109 / Chapter 5.5.2 --- Pin Count Limitation --- p.110 / Chapter 5.5.3 --- Speed Limitation --- p.111 / Chapter 5.5.4 --- Other Design Considerations --- p.111 / Chapter 5.6 --- Discussions --- p.112 / Chapter 6 --- Dynamic Priority Schemes for Fast Packet Switches --- p.114 / Chapter 6.1 --- Motivation --- p.114 / Chapter 6.2 --- Switch Architecture --- p.118 / Chapter 6.3 --- QCPD: Queueing Controlled Priority Discipline --- p.121 / Chapter 6.3.1 --- Algorithm QCPD --- p.121 / Chapter 6.4 --- BCPD: Blocking Controlled Priority Discipline --- p.122 / Chapter 6.4.1 --- Algorithm BCPD_FT --- p.122 / Chapter 6.4.2 --- Delay Guarantee by Algorithm BCPD_FT --- p.123 / Chapter 6.4.3 --- Algorithm BCPD_DT --- p.126 / Chapter 6.4.4 --- Delay Guarantee by Algorithm BCPD_DT --- p.128 / Chapter 6.5 --- HCPD: Hybrid Controlled Priority Discipline --- p.134 / Chapter 6.5.1 --- Algorithms HCPD_FT and HCPD_DT --- p.135 / Chapter 6.6 --- Performance Studies --- p.136 / Chapter 6.6.1 --- Performance Comparison of the Priority Schemes --- p.136 / Chapter 6.6.2 --- Cell Loss Performance of HCPD_DT --- p.140 / Chapter 6.6.3 --- Input Queue Distribution of HCPD_DT --- p.142 / Chapter 6.6.4 --- Delay Bound of HCPD_DT --- p.144 / Chapter 6.6.5 --- Performance of HCPD_DT under Priority Traffic --- p.148 / Chapter 6.7 --- The use of HCPD_DT in Pipeline Banyan --- p.152 / Chapter 6.8 --- Conclusion --- p.153 / Chapter 7 --- Summary and Future Work --- p.155 / Chapter 7.1 --- Summary --- p.155 / Chapter 7.2 --- Future Work --- p.156 / Chapter A --- Verilog HDL descriptions of 16x16 Pipeline Banyan --- p.158 / Chapter B --- User's Guide of 16x16 Pipeline Banyan Chip Set --- p.182 / Chapter B.l --- Specification --- p.182 / Chapter B.2 --- Control Plane Chip and Data Plane Chip Pinout --- p.183 / Chapter B.2.1 --- Control Plane Chip Pinout --- p.183 / Chapter B.2.2 --- Data Plane Chip Pinout --- p.183 / Chapter B.3 --- Signal Descriptions --- p.186 / Chapter B.3.1 --- Signal Descriptions of Control Plane Chip --- p.186 / Chapter B.3.2 --- Signal Descriptions of Data Plane Chip --- p.187 / Chapter B.4 --- Connection Examples --- p.188 / Bibliography --- p.191
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_318249 |
| Date | January 1994 |
| Contributors | Yeung, Ming Sang., Chinese University of Hong Kong Graduate School. Division of Information Engineering. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, ix, 191, [10] leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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