by Lam Chin Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1990. / Bibliography: leaves 167-174. / ABSTRACT --- p.1 / ACKNOWLEDGEMENTS --- p.2 / TABLE OF CONTENTS --- p.3 / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Gaining performance with multiprocessing --- p.1 / Chapter 1.1.1 --- Software approach --- p.2 / Chapter 1.1.2 --- hardware approach --- p.2 / Chapter 1.2 --- Parallel processing --- p.4 / Chapter 1.3 --- Gaining performance with multiprocessing --- p.7 / Chapter 1.3.1 --- Multiprocessor configurations --- p.7 / Chapter 1.3.2 --- Multiprocessor design issues --- p.9 / Chapter 1.3.3 --- Using microprocessors --- p.11 / Chapter 1.3.4 --- Bus based systems --- p.12 / Chapter 1.4 --- Shared memory and message passing --- p.13 / Chapter 1.4.1 --- Shared memory --- p.13 / Chapter 1.4.2 --- Message passing --- p.14 / Chapter 1.4.3 --- Comparisons of the two paradigms --- p.16 / Chapter 1.5 --- Summary and comment --- p.19 / Chapter CHAPTER 2 --- AN OVERVIEW OF COMMON APPROACHES --- p.20 / Chapter 2.1 --- SUPRENUM --- p.20 / Chapter 2.2 --- MEMSY --- p.22 / Chapter 2.3 --- ELXSI --- p.24 / Chapter 2.4 --- Sequent --- p.25 / Chapter 2.5 --- YACKOS --- p.26 / Chapter 2.6 --- Summary --- p.30 / Chapter CHAPTER 3 --- THE MPC APPROACH --- p.32 / Chapter 3.1 --- A shared memory multiprocessor architecture --- p.32 / Chapter 3.2 --- Message passer for inter-process communication --- p.32 / Chapter 3.2.1 --- A review of the message passer approach --- p.33 / Chapter 3.2.2 --- Pit-falls of the message passer approach --- p.34 / Chapter 3.3 --- The role of the MPC --- p.35 / Chapter 3.3.1 --- The quest for the MPC --- p.35 / Chapter 3.3.2 --- Duties of the MPC --- p.37 / Chapter 3.3.2.1 --- Software aspects --- p.37 / Chapter 3.3.2.2 --- Hardware aspects --- p.40 / Chapter 3.4 --- Advantages and disadvantages --- p.41 / Chapter 3.4.1 --- Advantages --- p.41 / Chapter 3.4.2 --- Disadvantages --- p.43 / Chapter 3.4.3 --- Other discussions --- p.44 / Chapter 3.5 --- Summary --- p.44 / Chapter CHAPTER 4 --- THE DESIGN OF SM3 --- p.46 / Chapter 4.1 --- Introduction to SM3 --- p.45 / Chapter 4.2 --- Software aspects --- p.47 / Chapter 4.2.1 --- Programming model --- p.48 / Chapter 4.2.1.1 --- Logical entities --- p.48 / Chapter 4.2.1.2 --- Communication procedure --- p.48 / Chapter 4.2.2 --- Message structure --- p.51 / Chapter 4.2.2.1 --- Broadcast versus point-to-point messages --- p.52 / Chapter 4.2.2.2 --- Message priority --- p.52 / Chapter 4.2.2.3 --- Blocking versus non-blocking --- p.53 / Chapter 4.3 --- Hardware aspects --- p.55 / Chapter 4.3.1 --- Overall architecture --- p.55 / Chapter 4.3.2 --- The host machine / Chapter 4.3.3 --- Slave processor nodes --- p.57 / Chapter 4.3.4 --- The MPC --- p.59 / Chapter 4.4 --- Communication protocols --- p.60 / Chapter 4.4.1 --- Short and long messages --- p.60 / Chapter 4.4.2 --- Point-to-point messages --- p.61 / Chapter 4.4.3 --- 1-to-N DMA for broadcast messages --- p.63 / Chapter 4.4.3.1 --- Introducing 1-to-N DMA --- p.63 / Chapter 4.4.3.2 --- 1-to-N DMA operation --- p.64 / Chapter 4.4.3.3 --- Merits and demerits of 1-to-N DMA --- p.67 / Chapter 4.5 --- Summary --- p.68 / Chapter CHAPTER 5 --- IMPLEMENTATION ISSUES OF SM3 --- p.70 / Chapter 5.1 --- The shared bus - VMEbus --- p.70 / Chapter 5.1.1 --- Why VMEbus --- p.70 / Chapter 5.1.2 --- Customizing the VMEbus --- p.71 / Chapter 5.2 --- The host machine --- p.71 / Chapter 5.3 --- Slave processor nodes --- p.72 / Chapter 5.3.1 --- Overview of a PN --- p.74 / Chapter 5.3.2 --- The MC68030 microprocessor --- p.77 / Chapter 5.3.3 --- The DMAC M68442 --- p.78 / Chapter 5.3.4 --- Registers --- p.79 / Chapter 5.3.5 --- Shared-bus interface --- p.80 / Chapter 5.3.6 --- Communication logic --- p.80 / Chapter 5.4 --- The MPC --- p.80 / Chapter 5.4.1 --- Overview of the MPC --- p.81 / Chapter 5.4.2 --- Registers --- p.81 / Chapter 5.4.3 --- Communication logic --- p.83 / Chapter 5.5 --- Protocol implementation --- p.84 / Chapter 5.5.1 --- Point-to-point messages --- p.84 / Chapter 5.5.2 --- Broadcast messages --- p.86 / Chapter 5.5.2.1 --- Circular buffer queue --- p.87 / Chapter 5.5.2.2 --- Participating entities --- p.87 / Chapter 5.5.2.3 --- Protocol details --- p.88 / Chapter 5.6 --- System start-up procedure --- p.94 / Chapter 5.6.1 --- Power up reset of PNs --- p.94 / Chapter 5.6.2 --- Initialization of the processor pool --- p.95 / Chapter 5.7 --- Summary --- p.95 / Chapter CHAPTER 6 --- APPLICATION EXAMPLES --- p.96 / Chapter 6.1 --- Introduction --- p.96 / Chapter 6.2 --- Matrix Multiplication --- p.96 / Chapter 6.3 --- Parallel Quicksort --- p.97 / Chapter 6.4 --- Pipeline Problems --- p.99 / Chapter CHAPTER 7 --- UNSOLVED PROBLEMS AND FUTURE DEVELOPMENT --- p.101 / Chapter 7.1 --- Current Status --- p.101 / Chapter 7.2 --- Possible immediate enhancements --- p.102 / Chapter 7.2.1 --- Enhancement to the PNs --- p.102 / Chapter 7.2.2 --- Enhancement of the MPC --- p.103 / Chapter 7.2.3 --- Communication kernel enhancement --- p.103 / Chapter 7.3 --- Limitation of a shared bus --- p.104 / Chapter 7.4 --- Number crunching capability --- p.105 / Chapter 7.5 --- Parallel programming environment --- p.105 / Chapter 7.5.1 --- Conform to serial language --- p.105 / Chapter 7.5.2 --- Moving to parallel programming languages --- p.106 / Chapter 7.5.2.1 --- Uni-processor Unix --- p.107 / Chapter 7.5.2.2 --- Porting Unix --- p.108 / Chapter 7.5.2.3 --- Multiprocessor Unix --- p.108 / Chapter 7.5.3 --- Object-oriented approach --- p.110 / Chapter 7.6 --- Summary --- p.112 / Chapter CHAPTER 8 --- CONCLUSION --- p.113 / Chapter 8.1 --- Thesis summary --- p.113 / Chapter 8.2 --- Author's comment --- p.114 / Chapter 8.3 --- Looking into the future --- p.116 / Chapter APPENDIX A --- BLOCK DIAGRAM --- p.117 / Chapter APPENDIX B --- CIRCUIT DIAGRAMS --- p.119 / Chapter APPENDIX C --- PCB LAYOUT --- p.126 / Chapter APPENDIX D --- VMEBUS ADDRESS MAP --- p.132 / Chapter APPENDIX E --- PROCESSOR NODE ADDRESS MAP --- p.133 / Chapter APPENDIX F --- REGISTER LAYOUT --- p.134 / Chapter F.1 --- Registers on a PN --- p.134 / Chapter F.2 --- Registers on the MPC --- p.134 / Chapter APPENDIX G --- PAL DESIGN --- p.136 / Chapter APPENDIX H --- COMMUNICATION SUB-BUS --- p.146 / Chapter H.1 --- Signal definition --- p.146 / Chapter H.2 --- Pin assignment --- p.146 / Chapter APPENDIX I --- FEASIBILITY OF TASK DISTRIBUTION PLAN --- p.147 / Chapter APPENDIX J --- COMMUNICATION PRIMITIVES --- p.148 / Chapter APPENDIX K --- PHOTOGRAPHS OF SM3 --- p.150 / Chapter APPENDIX L --- PROTOCOL STATE DIAGRAMS --- p.152 / Chapter L.1 --- Predefined partial state diagrams --- p.152 / Chapter L.2 --- Point-to-point messages --- p.152 / Chapter L.3 --- Broadcast messages --- p.154 / Chapter APPENDIX M --- BOOT-UP PROCEDURE OF SM3 --- p.159 / PUBLICATIONS --- p.161 / REFERENCES --- p.162
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_318578 |
| Date | January 1990 |
| Contributors | Lam, Chin Hung., Chinese University of Hong Kong Graduate School. Division of Computer Science. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, 174 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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