by Hon-Kai, Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 102-105). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Scheduling In Real-time Systems --- p.4 / Chapter 1.3 --- Cache Memories --- p.5 / Chapter 1.4 --- Outline Of The Dissertation --- p.8 / Chapter 2 --- Related Work --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- Predictable Cache Designs --- p.9 / Chapter 2.2.1 --- Locking Cache Lines Design --- p.9 / Chapter 2.2.2 --- Partially Dynamic And Static Cache Partition Allocation Design --- p.10 / Chapter 2.2.3 --- SMART (Strategic Memory Allocation for Real Time) Cache Design --- p.10 / Chapter 2.3 --- Prefetching --- p.11 / Chapter 2.3.1 --- Introduction --- p.11 / Chapter 2.3.2 --- Hardware Support Prefetching --- p.12 / Chapter 2.3.3 --- Software Assisted Prefetching --- p.12 / Chapter 2.3.4 --- Partial Cache Hit --- p.13 / Chapter 2.3.5 --- Cache Pollution Problems --- p.13 / Chapter 2.4 --- Cache Line Replacement Policies --- p.13 / Chapter 2.5 --- Main Memory Update Policies --- p.14 / Chapter 2.6 --- Summaries --- p.15 / Chapter 3 --- Problems And Motivations --- p.16 / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Problems --- p.16 / Chapter 3.2.1 --- Modern Cache Architecture Is Inappropriate For Real-time Systems --- p.16 / Chapter 3.2.2 --- Intertask Interference: The Effects Of Preemption --- p.17 / Chapter 3.2.3 --- Intratask Interference: Cache Line Collision --- p.20 / Chapter 3.3 --- Motivations --- p.21 / Chapter 3.3.1 --- Improvement Of The Cache Performance In Real-time Systems --- p.21 / Chapter 3.3.2 --- Hiding of Preemption Effects --- p.22 / Chapter 3.4 --- Conclusions --- p.25 / Chapter 4 --- Proposed Real-Time Cache Design --- p.26 / Chapter 4.1 --- Introduction --- p.26 / Chapter 4.2 --- Concepts Definition --- p.26 / Chapter 4.2.1 --- Tasks Definition --- p.26 / Chapter 4.2.2 --- Cache Performance Values --- p.27 / Chapter 4.3 --- Issues Related To Proposed Real-Time Cache Design --- p.28 / Chapter 4.3.1 --- A Task Serving Policy --- p.30 / Chapter 4.3.2 --- Number Of Private And Shared Cache Partitions --- p.31 / Chapter 4.3.3 --- Controlling The Cache Partitions: Cache Partition Table And Pro- cess Info Table --- p.32 / Chapter 4.3.4 --- Re-organization Of Task Owns Cache Partition(s) --- p.34 / Chapter 4.3.5 --- Handling The Bus Bandwidth: Memory Requests Queue ( MRQ ) --- p.35 / Chapter 4.3.6 --- How To Address The Cache Models --- p.37 / Chapter 4.3.7 --- Data Coherence Problems For Partitioned Cache Model And Non- partitioned Cache Model --- p.39 / Chapter 4.4 --- Mechanism For Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.1 --- Basic Operation Of Proposed Real-Time Cache Design --- p.43 / Chapter 4.4.2 --- Assumptions And Rules --- p.43 / Chapter 4.4.3 --- First Round Dynamic Cache Partition Re-allocation --- p.44 / Chapter 4.4.4 --- Later Round Dynamic Cache Partition Re-allocation --- p.45 / Chapter 5 --- Simulation Environments --- p.56 / Chapter 5.1 --- Proposed Architectural Model --- p.56 / Chapter 5.2 --- Working Environment For Proposed Real-time Cache Models --- p.57 / Chapter 5.2.1 --- Cost Model --- p.57 / Chapter 5.2.2 --- System Model --- p.64 / Chapter 5.2.3 --- Fair Comparsion Between The Unified Cache And The Separate Caches --- p.64 / Chapter 5.2.4 --- Operations Within The Preemption --- p.65 / Chapter 5.3 --- Benchmark Programs --- p.65 / Chapter 5.3.1 --- The NASA7 Benchmark --- p.66 / Chapter 5.3.2 --- The SU2COR Benchmark --- p.66 / Chapter 5.3.3 --- The TOMCATV Benchmark --- p.66 / Chapter 5.3.4 --- The WAVE5 Benchmark --- p.67 / Chapter 5.3.5 --- The COMPRESS Benchmark --- p.67 / Chapter 5.3.6 --- The ESPRESSO Benchmark --- p.68 / Chapter 5.4 --- Simulations Parameters --- p.68 / Chapter 6 --- Analysis Of Simulations --- p.71 / Chapter 6.1 --- Introduction --- p.71 / Chapter 6.2 --- Trace Files Statistics --- p.71 / Chapter 6.3 --- Interpretation Of Partial Cache Hit --- p.72 / Chapter 6.4 --- The Effects Of Cache Size --- p.72 / Chapter 6.4.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.72 / Chapter 6.5 --- The Effects Of Cache Partition Size --- p.76 / Chapter 6.5.1 --- Performance Of Model 3 --- p.79 / Chapter 6.5.2 --- Performance Of Model 1 --- p.79 / Chapter 6.6 --- The Effects Of Line Size --- p.80 / Chapter 6.6.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.80 / Chapter 6.7 --- The Effects Of Set Associativity --- p.83 / Chapter 6.7.1 --- "Performance Of Model 1, Model 2, Model 3 And Model 4" --- p.83 / Chapter 6.8 --- The Effects Of The Best-expected Cache Performance --- p.84 / Chapter 6.8.1 --- Performance of Model 1 --- p.87 / Chapter 6.8.2 --- Performance of Model 3 --- p.88 / Chapter 6.9 --- The Effects Of The Standard-expected Cache Performance --- p.89 / Chapter 6.9.1 --- Performance Of Model 1 --- p.89 / Chapter 6.9.2 --- Performance Of Model 3 --- p.91 / Chapter 6.10 --- The Effects Of Cycle Execution Time/Cycle Deadline Period --- p.92 / Chapter 6.10.1 --- "Performances Of Model 1, Model 2, Model 3 And Model 4" --- p.92 / Chapter 7 --- Conclusions And Future Work --- p.95 / Chapter 7.1 --- Conclusions --- p.95 / Chapter 7.1.1 --- Unified Cache Model Is More Suitable In Real-time Systems --- p.99 / Chapter 7.1.2 --- Comments On Aperiodic Tasks --- p.100 / Chapter 7.2 --- Future Work --- p.100
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_321557 |
| Date | January 1996 |
| Contributors | Cheung, Hon-Kai., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Publisher | Chinese University of Hong Kong |
| Source Sets | The Chinese University of Hong Kong |
| Language | English |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, x, 105 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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