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Implementation of an FPGA based accelerator for virtual private networks.

Cheung Yu Hoi Ocean. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 65-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.2 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Outline --- p.3 / Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4 / Chapter 2.3 --- Secure Virtual Private Network --- p.6 / Chapter 2.4 --- LibDES --- p.9 / Chapter 2.5 --- FreeS/WAN --- p.9 / Chapter 2.6 --- Commercial VPN solutions --- p.9 / Chapter 2.7 --- Summary --- p.11 / Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12 / Chapter 3.1 --- Introduction --- p.12 / Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12 / Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14 / Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16 / Chapter 3.3 --- The IDEA Algorithm --- p.17 / Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20 / Chapter 3.3.2 --- Previous work on IDEA --- p.21 / Chapter 3.4 --- Block Cipher Modes of operation --- p.23 / Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23 / Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25 / Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27 / Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27 / Chapter 3.6 --- Pilchard --- p.30 / Chapter 3.6.1 --- Memory Cache Control Mode --- p.31 / Chapter 3.7 --- Electronic Design Automation Tools --- p.32 / Chapter 3.8 --- Summary --- p.33 / Chapter 4 --- Implementation / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Hardware Platform --- p.36 / Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36 / Chapter 4.1.3 --- Pilchard Software --- p.38 / Chapter 4.2 --- DES in ECB mode --- p.39 / Chapter 4.2.1 --- Hardware --- p.39 / Chapter 4.2.2 --- Software Interface --- p.40 / Chapter 4.3 --- DES in CBC mode --- p.42 / Chapter 4.3.1 --- Hardware --- p.42 / Chapter 4.3.2 --- Software Interface --- p.42 / Chapter 4.4 --- Triple-DES in CBC mode --- p.45 / Chapter 4.4.1 --- Hardware --- p.45 / Chapter 4.4.2 --- Software Interface --- p.45 / Chapter 4.5 --- IDEA in ECB mode --- p.48 / Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48 / Chapter 4.5.2 --- Hardware --- p.48 / Chapter 4.5.3 --- Software Interface --- p.50 / Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51 / Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52 / Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53 / Chapter 4.9 --- Summary --- p.54 / Chapter 5 --- Results --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Benchmarking environment --- p.55 / Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56 / Chapter 5.3.1 --- Performance of Triple-DES core --- p.55 / Chapter 5.3.2 --- Performance of IDEA core --- p.58 / Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59 / Chapter 5.4.1 --- Triple-DES --- p.59 / Chapter 5.4.2 --- IDEA --- p.60 / Chapter 5.5 --- Summary --- p.61 / Chapter 6 --- Conclusion --- p.62 / Chapter 6.1 --- Future development --- p.63 / Bibliography --- p.65

Identiferoai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_323823
Date January 2002
ContributorsCheung, Yu Hoi Ocean., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering.
Source SetsThe Chinese University of Hong Kong
LanguageEnglish, Chinese
Detected LanguageEnglish
TypeText, bibliography
Formatprint, ix, 71 leaves : ill. ; 30 cm.
RightsUse of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/)

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