by Cheng Wang-tung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 97-99). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.i / Acknowledgements --- p.ii / Table of Contents --- p.iii / List of Figures --- p.vii / List of Tables --- p.xi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Objective --- p.4 / Chapter 1.3 --- Outline --- p.4 / Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6 / Chapter 2.3 --- Theory of ΣΔ modulation --- p.6 / Chapter 2.3.1 --- Quantization noise --- p.7 / Chapter 2.3.2 --- Oversampling --- p.8 / Chapter 2.3.3 --- Noise Shaping --- p.9 / Chapter 2.3.4 --- Performance Parameter --- p.11 / Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11 / Chapter 2.3.6 --- Case Study --- p.12 / Chapter 2.3.6.1 --- Transfer Function --- p.12 / Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13 / Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14 / Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15 / Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18 / Chapter 2.5.1 --- Quadrature signal --- p.18 / Chapter 2.5.2 --- I/Q Modulation --- p.19 / Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21 / Chapter 2.6.1 --- High Level Simulation --- p.23 / Chapter 2.6.2 --- Discussion --- p.26 / Chapter 2.7 --- Summary --- p.27 / Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28 / Chapter 3.2.1 --- Principle of Operation --- p.30 / Chapter 3.3 --- Justification of the Proposed Idea --- p.35 / Chapter 3.4 --- Summary --- p.37 / Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Design of ΣΔ Modulator --- p.39 / Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40 / Chapter 4.3 --- Design of Operational Amplifier --- p.45 / Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45 / Chapter 4.3.2 --- Common Mode feedback --- p.47 / Chapter 4.3.3 --- Bias Circuit --- p.49 / Chapter 4.3.4 --- Simulation Results --- p.50 / Chapter 4.4 --- Design of Comparator --- p.54 / Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54 / Chapter 4.4.2 --- Simulation Results --- p.55 / Chapter 4.5 --- Design of Clock Generator --- p.56 / Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57 / Chapter 4.5.2 --- Simulation Results --- p.58 / Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59 / Chapter 4.7 --- Simulation Results --- p.61 / Chapter 4.7.1 --- Proposed Architecture --- p.62 / Chapter 4.7.2 --- Traditional Architecture --- p.62 / Chapter 4.8 --- Summary --- p.63 / Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Common-Centroid Structure --- p.65 / Chapter 5.3 --- Shielding Technique --- p.67 / Chapter 5.3.1 --- Shielding of device by substrate --- p.67 / Chapter 5.3.2 --- Floor Planning --- p.68 / Chapter 5.4 --- Layout of Power Rail --- p.69 / Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70 / Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74 / Chapter 5.6.1 --- Proposed Architecture --- p.75 / Chapter 5.6.2 --- Traditional Architecture --- p.77 / Chapter 5.7 --- Summary --- p.79 / Chapter Chapter 6 --- Measurement Results --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Considerations of PCB Design --- p.82 / Chapter 6.3 --- Measurement Setup --- p.83 / Chapter 6.4 --- Measurement Results --- p.85 / Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85 / Chapter 6.5 --- Summary --- p.92 / Chapter Chapter 7 --- Conclusion --- p.95 / Chapter 7.1 --- Conclusion --- p.95 / Chapter 7.2 --- Future Works --- p.96 / References --- p.97 / Appendix --- p.100 / Chapter A.1 --- Publications --- p.100 / Chapter A.2 --- Schematic of proposed front end --- p.101 / Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102 / Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103 / Chapter A.5 --- Schematic of biasing circuit --- p.104 / Chapter A.6 --- Schematic of preamplifier in comparator --- p.105 / Chapter A.7 --- Schematic of latched part in comparator --- p.106 / Chapter A.8 --- Schematic of the clock generator --- p.107
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_324949 |
| Date | January 2004 |
| Contributors | Cheng, Wang-tung., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xii, 107 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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