So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_325198 |
| Date | January 2005 |
| Contributors | So, Pui Tak., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, 1 v. (various pagings) : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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