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Variable block size motion estimation hardware for video encoders.

Li, Man Ho. / Thesis submitted in: November 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 137-143). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.3 / Chapter 1.2 --- The objectives of this thesis --- p.4 / Chapter 1.3 --- Contributions --- p.5 / Chapter 1.4 --- Thesis structure --- p.6 / Chapter 2 --- Digital video compression --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Fundamentals of lossy video compression --- p.9 / Chapter 2.2.1 --- Video compression and human visual systems --- p.10 / Chapter 2.2.2 --- Representation of color --- p.10 / Chapter 2.2.3 --- Sampling methods - frames and fields --- p.11 / Chapter 2.2.4 --- Compression methods --- p.11 / Chapter 2.2.5 --- Motion estimation --- p.12 / Chapter 2.2.6 --- Motion compensation --- p.13 / Chapter 2.2.7 --- Transform --- p.13 / Chapter 2.2.8 --- Quantization --- p.14 / Chapter 2.2.9 --- Entropy Encoding --- p.14 / Chapter 2.2.10 --- Intra-prediction unit --- p.14 / Chapter 2.2.11 --- Deblocking filter --- p.15 / Chapter 2.2.12 --- Complexity analysis of on different com- pression stages --- p.16 / Chapter 2.3 --- Motion estimation process --- p.16 / Chapter 2.3.1 --- Block-based matching method --- p.16 / Chapter 2.3.2 --- Motion estimation procedure --- p.18 / Chapter 2.3.3 --- Matching Criteria --- p.19 / Chapter 2.3.4 --- Motion vectors --- p.21 / Chapter 2.3.5 --- Quality judgment --- p.22 / Chapter 2.4 --- Block-based matching algorithms for motion estimation --- p.23 / Chapter 2.4.1 --- Full search (FS) --- p.23 / Chapter 2.4.2 --- Three-step search (TSS) --- p.24 / Chapter 2.4.3 --- Two-dimensional Logarithmic Search Algorithm (2D-log search) --- p.25 / Chapter 2.4.4 --- Diamond Search (DS) --- p.25 / Chapter 2.4.5 --- Fast full search (FFS) --- p.26 / Chapter 2.5 --- Complexity analysis of motion estimation --- p.27 / Chapter 2.5.1 --- Different searching algorithms --- p.28 / Chapter 2.5.2 --- Fixed-block size motion estimation --- p.28 / Chapter 2.5.3 --- Variable block size motion estimation --- p.29 / Chapter 2.5.4 --- Sub-pixel motion estimation --- p.30 / Chapter 2.5.5 --- Multi-reference frame motion estimation . --- p.30 / Chapter 2.6 --- Picture quality analysis --- p.31 / Chapter 2.7 --- Summary --- p.32 / Chapter 3 --- Arithmetic for video encoding --- p.33 / Chapter 3.1 --- Introduction --- p.33 / Chapter 3.2 --- Number systems --- p.34 / Chapter 3.2.1 --- Non-redundant Number System --- p.34 / Chapter 3.2.2 --- Redundant number system --- p.36 / Chapter 3.3 --- Addition/subtraction algorithm --- p.38 / Chapter 3.3.1 --- Non-redundant number addition --- p.39 / Chapter 3.3.2 --- Carry-save number addition --- p.39 / Chapter 3.3.3 --- Signed-digit number addition --- p.40 / Chapter 3.4 --- Bit-serial algorithms --- p.42 / Chapter 3.4.1 --- Least-significant-bit (LSB) first mode --- p.42 / Chapter 3.4.2 --- Most-significant-bit (MSB) first mode --- p.43 / Chapter 3.5 --- Absolute difference algorithm --- p.44 / Chapter 3.5.1 --- Non-redundant algorithm for absolute difference --- p.44 / Chapter 3.5.2 --- Redundant algorithm for absolute difference --- p.45 / Chapter 3.6 --- Multi-operand addition algorithm --- p.47 / Chapter 3.6.1 --- Bit-parallel non-redundant adder tree implementation --- p.47 / Chapter 3.6.2 --- Bit-parallel carry-save adder tree implementation --- p.49 / Chapter 3.6.3 --- Bit serial signed digit adder tree implementation --- p.49 / Chapter 3.7 --- Comparison algorithms --- p.50 / Chapter 3.7.1 --- Non-redundant comparison algorithm --- p.51 / Chapter 3.7.2 --- Signed-digit comparison algorithm --- p.52 / Chapter 3.8 --- Summary --- p.53 / Chapter 4 --- VLSI architectures for video encoding --- p.54 / Chapter 4.1 --- Introduction --- p.54 / Chapter 4.2 --- Implementation platform - (FPGA) --- p.55 / Chapter 4.2.1 --- Basic FPGA architecture --- p.55 / Chapter 4.2.2 --- DSP blocks in FPGA device --- p.56 / Chapter 4.2.3 --- Advantages employing FPGA --- p.57 / Chapter 4.2.4 --- Commercial FPGA Device --- p.58 / Chapter 4.3 --- Top level architecture of motion estimation processor --- p.59 / Chapter 4.4 --- Bit-parallel architectures for motion estimation --- p.60 / Chapter 4.4.1 --- Systolic arrays --- p.60 / Chapter 4.4.2 --- Mapping of a motion estimation algorithm onto systolic array --- p.61 / Chapter 4.4.3 --- 1-D systolic array architecture (LA-ID) --- p.63 / Chapter 4.4.4 --- 2-D systolic array architecture (LA-2D) --- p.64 / Chapter 4.4.5 --- 1-D Tree architecture (GA-1D) --- p.64 / Chapter 4.4.6 --- 2-D Tree architecture (GA-2D) --- p.65 / Chapter 4.4.7 --- Variable block size support in bit-parallel architectures --- p.66 / Chapter 4.5 --- Bit-serial motion estimation architecture --- p.68 / Chapter 4.5.1 --- Data Processing Direction --- p.68 / Chapter 4.5.2 --- Algorithm mapping and dataflow design . --- p.68 / Chapter 4.5.3 --- Early termination scheme --- p.69 / Chapter 4.5.4 --- Top-level architecture --- p.70 / Chapter 4.5.5 --- Non redundant positive number to signed digit conversion --- p.71 / Chapter 4.5.6 --- Signed-digit adder tree --- p.73 / Chapter 4.5.7 --- SAD merger --- p.74 / Chapter 4.5.8 --- Signed-digit comparator --- p.75 / Chapter 4.5.9 --- Early termination controller --- p.76 / Chapter 4.5.10 --- Data scheduling and timeline --- p.80 / Chapter 4.6 --- Decision metric in different architectural types . . --- p.80 / Chapter 4.6.1 --- Throughput --- p.81 / Chapter 4.6.2 --- Memory bandwidth --- p.83 / Chapter 4.6.3 --- Silicon area occupied and power consump- tion --- p.83 / Chapter 4.7 --- Architecture selection for different applications . . --- p.84 / Chapter 4.7.1 --- CIF and QCIF resolution --- p.84 / Chapter 4.7.2 --- SDTV resolution --- p.85 / Chapter 4.7.3 --- HDTV resolution --- p.85 / Chapter 4.8 --- Summary --- p.86 / Chapter 5 --- Results and comparison --- p.87 / Chapter 5.1 --- Introduction --- p.87 / Chapter 5.2 --- Implementation details --- p.87 / Chapter 5.2.1 --- Bit-parallel 1-D systolic array --- p.88 / Chapter 5.2.2 --- Bit-parallel 2-D systolic array --- p.89 / Chapter 5.2.3 --- Bit-parallel Tree architecture --- p.90 / Chapter 5.2.4 --- MSB-first bit-serial design --- p.91 / Chapter 5.3 --- Comparison between motion estimation architectures --- p.93 / Chapter 5.3.1 --- Throughput and latency --- p.93 / Chapter 5.3.2 --- Occupied resources --- p.94 / Chapter 5.3.3 --- Memory bandwidth --- p.95 / Chapter 5.3.4 --- Motion estimation algorithm --- p.95 / Chapter 5.3.5 --- Power consumption --- p.97 / Chapter 5.4 --- Comparison to ASIC and FPGA architectures in past literature --- p.99 / Chapter 5.5 --- Summary --- p.101 / Chapter 6 --- Conclusion --- p.102 / Chapter 6.1 --- Summary --- p.102 / Chapter 6.1.1 --- Algorithmic optimizations --- p.102 / Chapter 6.1.2 --- Architecture and arithmetic optimizations --- p.103 / Chapter 6.1.3 --- Implementation on a FPGA platform . . . --- p.104 / Chapter 6.2 --- Future work --- p.106 / Chapter A --- VHDL Sources --- p.108 / Chapter A.1 --- Online Full Adder --- p.108 / Chapter A.2 --- Online Signed Digit Full Adder --- p.109 / Chapter A.3 --- Online Pull Adder Tree --- p.110 / Chapter A.4 --- SAD merger --- p.112 / Chapter A.5 --- Signed digit adder tree stage (top) --- p.116 / Chapter A.6 --- Absolute element --- p.118 / Chapter A.7 --- Absolute stage (top) --- p.119 / Chapter A.8 --- Online comparator element --- p.120 / Chapter A.9 --- Comparator stage (top) --- p.122 / Chapter A.10 --- MSB-first motion estimation processor --- p.134 / Bibliography --- p.137

Identiferoai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_325865
Date January 2007
ContributorsLi, Man Ho., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering.
Source SetsThe Chinese University of Hong Kong
LanguageEnglish, Chinese
Detected LanguageEnglish
TypeText, bibliography
Formatprint, xv, 143 leaves : ill. ; 30 cm.
RightsUse of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/)

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