Research on heterojunction (HJ) metal oxide thin film transistors (TFTs) has accelerated remarkably over the last decade due to their superior performance over their conventional single-layer (SL) counterparts. Promising results in laboratory-scale demonstrations have further triggered an increased number of investigations into fabrication and processing techniques for the large-scale integration of HJ metal oxide TFTs. Nevertheless, a lack of consensus regarding the most appropriate scalable manufacturing technique, which combines low-cost and high-throughput fabrication, holds back new opportunities for HJ metal oxide TFTs in emerging applications. In this thesis, novel approaches and strategies are introduced to facilitate the large-scale integration of HJ metal oxide TFTs.
The first study of this dissertation introduces the solution-processed In2O3/ZnO heterojunction TFTs with a high-κ bilayer dielectric consisting of Al2O3/ZrO2. Processing was carried out on rigid glass as well as flexible PEN substrates via rapid flash lamp annealing (FLA) as an alternative scalable and high-throughput processing route to conventional thermal annealing.
In the second study of the dissertation, a novel 3D/2D/3D mixed-dimensional channel concept was developed with the combination of scalable spray coating and FLA techniques. The insertion of sprayed MoS2 nanoflakes between flashed SnO2/ZnO HJ results in outstanding device performance with a high mobility value of 62 cm2/Vs compared to single layers as well as heterojunction metal oxide TFTs, showing maximum mobility of 4.48 cm2/Vs.
In the third study, the fabrication of In2O3/ZnO heterojunction metal oxide TFTs with solution-processed conductive Ti3C2Tx MXene contacts using a processing route that fully relies on a scalable spray coating process is demonstrated as an alternative to low-throughput vacuum-based electrodes. Notably, the proposed approach was successfully upscaled to a 4-inch glass substrate, underlining the significant potential garnered by MXene electrodes for industrial-scale electronics.
The last study of the dissertation exploits the advantages of the adhesion-lithography (a-Lith) technique, which enables the development of coplanar self-aligned gate (SAG) In2O3/ZnO heterojunction TFTs and their facile integration into large-area electronics. Using the a-Lith technique, coplanar SAG architectures were fabricated where the gate and dielectric (Al and Al2O3, respectively) are located side by side with the source/drain electrodes (Au), separated from each other by nanogaps.
| Identifer | oai:union.ndltd.org:kaust.edu.sa/oai:repository.kaust.edu.sa:10754/691642 |
| Date | 03 May 2023 |
| Creators | Yarali, Emre |
| Contributors | Anthopoulos, Thomas D., Physical Science and Engineering (PSE) Division, Salama, Khaled N., Caironi, Mario, Tung, Vincent |
| Source Sets | King Abdullah University of Science and Technology |
| Language | English |
| Detected Language | English |
| Type | Dissertation |
| Rights | 2024-05-11, At the time of archiving, the student author of this dissertation opted to temporarily restrict access to it. The full text of this dissertation will become available to the public after the expiration of the embargo on 2024-05-11. |
| Relation | N/A |
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