The increase in solar energy installation capacity and the versatility of modern power inverters have enabled widespread penetration of distributed generation in modern power systems. Islanding detection techniques allow for fast identification and corrective action in the face of abnormal events. Current standards specify the operational limits for voltage, frequency, and detection time. Grid codes specify the procedures for disconnection to establish safe network maintenance conditions. Passive, active, and remote techniques require voltage, current, and frequency measurements and the definition of thresholds for detection. Operational parameters such as load mismatch and quality factors influence the detection capabilities. False-positive triggering due to grid transients can lead to unnecessary disconnection of distributed generation resources. Cybersecurity threats pose a critical challenge for power systems and can result in significant operational disruptions and security risks. In particular, when a power system initiates communication links between different nodes or ends, it becomes more vulnerable to various forms of cyber-attacks. As such, it is imperative to address the potential cybersecurity risks associated with communication links. Through a literature review, this work analyzes the performance of several islanding detection techniques and proposes a modified 9-bus benchmark system to verify the robustness of passive and active methods against false-positive detections upon severe grid-side transients. Furthermore, this thesis conducts a detailed analysis of cyber-attacks on the remote islanding detection technique, using a real-time simulator to assess the potential impact of such attacks on the technique's effectiveness by simulating various attack scenarios. The findings of this analysis can help power system operators to better protect their systems from cyber-attacks and ensure the reliable operation of their distributed generation resources. Moreover, it discusses a conceptual implementation of hardware-in-the-loop testing. The modeling of the systems is discussed. Guidelines and international standards are presented. Various setups for experimental work are suggested and implemented.
| Identifer | oai:union.ndltd.org:kaust.edu.sa/oai:repository.kaust.edu.sa:10754/691828 |
| Date | 05 1900 |
| Creators | Alsabban, Maha |
| Contributors | Ahmed, Shehab, Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division, Park, Shinkyu, Konstantinou, Charalambos |
| Source Sets | King Abdullah University of Science and Technology |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Rights | 2024-05-21, At the time of archiving, the student author of this thesis opted to temporarily restrict access to it. The full text of this thesis will become available to the public after the expiration of the embargo on 2024-05-21. |
| Relation | N/A |
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