付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(情報学) / 甲第23325号 / 情博第761号 / 新制||情||130(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 大木 英司, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM
| Identifer | oai:union.ndltd.org:kyoto-u.ac.jp/oai:repository.kulib.kyoto-u.ac.jp:2433/263786 |
| Date | 23 March 2021 |
| Creators | Xu, Hongjie |
| Contributors | 徐, 宏傑, シュウ, ホンジェ |
| Publisher | Kyoto University, 京都大学 |
| Source Sets | Kyoto University |
| Language | English |
| Detected Language | English |
| Type | doctoral thesis, Thesis or Dissertation |
| Rights | 1.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2021/06 2.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, MOSDA: On-chip Memory Optimized Sparse Deep Neural Network Accelerator with Efficient Index Matching, IEEE Open Journal of Circuits and Systems, 2020/12 3.Hongjie Xu, Jun Shiomi and Hidetoshi Onodera, On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation, The 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020/09 4.Hongjie Xu, Jun Shiomi, Tohru Ishihara and Hidetoshi Onodera, On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, vol E102-A, no 12, pp. 1741-1750, 2019/12 5.Hongjie Xu, Jun Shiomi, Tohru Ishihara, and Hidetoshi Onodera, Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 237 - 242, DOI: 10.1109/PATMOS.2018.8464141, 2018/07 |
| Relation | https://doi.org/10.1109/PATMOS.2018.8464141 |
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