This work deals with the influence of MDAC (multiplying DAC) resolution on basic blocks of pipelined AD converter. The MDAC was designed with 1,5 and 2,5 bits resolution structure using switched capacitor technique (SC) utilizing CMOS 0,7 m technology. Basic stages of this pipelined ADC are analyzed and compared.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:217879 |
| Date | January 2009 |
| Creators | Kledrowetz, Vilém |
| Contributors | Fujcik, Lukáš, Háze, Jiří |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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