The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switch is able to divide one data stream, created from ethernet frames to the two data streams with half data flow.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:219860 |
| Date | January 2012 |
| Creators | Toman, Jakub |
| Contributors | Bobula, Marek, Kubíček, Michal |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Czech |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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