The goal of this project is to design a signal and data logger, which captures analog and digital signals with very long record time. The device supports multichannel complex triggering, a real-time oscilloscope-like mode and an offline mode for analyzing of previously sampled data. This project contains detailed analysis of the topic, description of hardware and software solutions and used methods. The thesis also contains verification tests and measurements. This device will be mainly used for hardware debugging of microprocessor based applications.
| Identifer | oai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:220693 |
| Date | January 2014 |
| Creators | Borsányi, Tamás |
| Contributors | Vyskočil, Pavel, Kolouch, Jaromír |
| Publisher | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií |
| Source Sets | Czech ETDs |
| Language | Slovak |
| Detected Language | English |
| Type | info:eu-repo/semantics/masterThesis |
| Rights | info:eu-repo/semantics/restrictedAccess |
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