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Využití syntézy na systémové úrovni pro aplikace s platformou ZYNQ / Using High-Level Synthesis for ZYNQ Platform Applications

This work describes using High-Level Synthesis in image processing application. The application is for Xilinx ZYNQ platform. The source code of components for FPGA is written in C++ programming language. For High-Level Synthesis is used Xilinx Vivado HLS tool. In the application are designed and implemented Sobel filter, Median filter, Bilateral filter and architecture for AdaBoost classificator. The extension of this work is implemented the component for network traffic. The component finds the begin of the packet.

Identiferoai:union.ndltd.org:nusl.cz/oai:invenio.nusl.cz:234946
Date January 2015
CreatorsHusák, Jiří
ContributorsDrábek, Vladimír, Fučík, Otto
PublisherVysoké učení technické v Brně. Fakulta informačních technologií
Source SetsCzech ETDs
LanguageCzech
Detected LanguageEnglish
Typeinfo:eu-repo/semantics/masterThesis
Rightsinfo:eu-repo/semantics/restrictedAccess

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