Small signal stability has always been an important concern for analog designers.
Recent advances such as the Loop Finder algorithm allows designers to detect and
identify local, potentially unstable return loops without the need to identify and add
breakpoints. However, this method suffers from extremely high time and memory
complexity and thus cannot be scaled to very large analog circuits. In this research
work, we first take an in-depth look at the loop finder algorithm so as to identify
certain key enhancements that can be made to overcome these shortcomings. We
next propose pole discovery and impedance computation methods that address these
shortcomings by exploring only a certain region of interest in the s-plane. The reduced
time and memory complexity obtained via the new methodology allows us to extend
automatic stability checking to much larger circuits than was previously possible.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/148461 |
| Date | 14 March 2013 |
| Creators | Mukherjee, Parijat 1985- |
| Contributors | Li, Peng |
| Source Sets | Texas A and M University |
| Detected Language | English |
| Type | Thesis, text |
| Format | application/pdf |
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