Delay test in nano-scale VLSI circuits becomes more difficult with shrinking
technology feature sizes and rising clock frequencies. In this dissertation, we study three
challenging issues in delay test: fault modeling, variational delay evaluation and path
selection under process variation. Previous research of fault modeling on resistive spot
defects, such as resistive opens and bridges in the interconnect, and resistive shorts in
devices, lacked an accurate fault model. As a result it was difficult to perform fault
simulation and select the best vectors. Conventional methods to compute variational delay
under process variation are either slow or inaccurate. On the problem of path selection
under process variation, previous approaches either choose too many paths, or missed the
path that is necessary to be tested.
We present new solutions in this dissertation. A new fault model that clearly and
comprehensively expresses the relationship between electrical behaviors and resistive
spots is proposed. Then the effect of process variations on path delays is modeled with a
linear function and a fast method to compute coefficients of the linear function is also
derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while
the fault coverage is satisfied. The experimental results show that the new solutions are
efficient and accurate.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/3234 |
| Date | 12 April 2006 |
| Creators | Lu, Xiang |
| Contributors | Shi, Weiping |
| Publisher | Texas A&M University |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | 808672 bytes, electronic, application/pdf, born digital |
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