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Fault simulation and test generation for small delay faults

Delay faults are an increasingly important test challenge. Traditional delay fault
models are incomplete in that they model only a subset of delay defect behaviors. To
solve this problem, a more realistic delay fault model has been developed which models
delay faults caused by the combination of spot defects and parametric process variation.
According to the new model, a realistic delay fault coverage metric has been developed.
Traditional path delay fault coverage metrics result in unrealistically low fault coverage,
and the real test quality is not reflected. The new metric uses a statistical approach and the
simulation based fault coverage is consistent with silicon data. Fast simulation algorithms
are also included in this dissertation.
The new metric suggests that testing the K longest paths per gate (KLPG) has high
detection probability for small delay faults under process variation. In this dissertation, a
novel automatic test pattern generation (ATPG) methodology to find the K longest
testable paths through each gate for both combinational and sequential circuits is
presented. Many techniques are used to reduce search space and CPU time significantly.
Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288.
The ATPG methodology has been implemented on industrial designs. Speed binning
has been done on many devices and silicon data has shown significant benefit of the
KLPG test, compared to several traditional delay test approaches.

Identiferoai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/4966
Date25 April 2007
CreatorsQiu, Wangqi
ContributorsWalker, Duncan M. H.
PublisherTexas A&M University
Source SetsTexas A and M University
Languageen_US
Detected LanguageEnglish
TypeBook, Thesis, Electronic Dissertation, text
Format703413 bytes, electronic, application/pdf, born digital

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