With VLSI(very large scale integration) technology shrinking and frequency increasing,
the minimum feature size is smaller than sub-wavelength lithography wavelength,
and the manufacturing cost is significantly increasing in order to achieve a
good yield. Consequently design companies need to further lower power consumption.
All these factors bring new challenges; simulation and modeling need to handle
more design constraints, and need to work with modern manufacturing processes. In
this dissertation, algorithms and new methodology are presented for these problems:
(1) fast and accurate capacitance extraction, (2) capacitance extraction considering
lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access
memory) performance and yield, and (4) new physical synthesis optimization flow is
used to shed area and reduce the power consumption.
Interconnect parasitic extraction plays an important role in simulation, verification,
optimization. A fast and accurate parasitic extraction algorithm is always
important for a current design automation tool. In this dissertation, we propose a
new algorithm named HybCap to efficiently handle multiple planar, conformal or
embedded dielectric media. From experimental results, the new method is significantly
faster than the previous one, 77X speedup, and has a 99% memory savings
compared with FastCap and 2X speedup, and has an 80% memory savings compared
with PHiCap for complex dielectric media.
In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction)
flow, a modified LPE flow and fast algorithms for interconnect parasitic
extraction are proposed in this dissertation. Our methodology is efficient, compatible
with the existing design flow and has high accuracy.
With the new enhanced parasitic extraction flow, simulation of BEOL effect on
SRAM performance becomes possible. A SRAM simulation model with internal cell
interconnect RC parasitics is proposed in order to study the BEOL lithography impact.
The impact of BEOL variations on memory designs are systematically evaluated
in this dissertation. The results show the power estimation with our SRAM model is
more accurate.
Finally, a new optimization flow to shed area blow in the design synthesis flow
is proposed, which is one level beyond simulation and modeling to directly optimize
design, but is also built upon accurate simulations and modeling. Two simple, yet
efficient, buffering and gate sizing techniques are presented. On 20 industrial designs
in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8%
total area reduction, 10% wirelength reduction and 770 ps worst slack improvement
on average.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-05-7677 |
| Date | 2010 May 1900 |
| Creators | Zhou, Ying |
| Contributors | Shi, Weiping |
| Source Sets | Texas A and M University |
| Language | English |
| Detected Language | English |
| Type | Book, Thesis, Electronic Dissertation, text |
| Format | application/pdf |
Page generated in 0.002 seconds