A Verilog HDL digital circuit fault simulator to detect permanent stuck-at logic faults for embedded cores-based synchronous sequential circuits is proposed in this thesis. The fault simulator can emulate a typical built-in self-testing (BIST) environment that utilizes a test pattern generator that sends its outputs to a module under test (MUT), with the resulting output from the MUT being fed into a test data analyzer. A fault is detected if the module response is different from that of the fault-free MUT. The fault simulator is suitable for testing synchronous sequential circuits described at the gate and flip-flop level in Verilog HDL. The subject thesis describes the detailed architecture and implementation of the fault simulator. Some simulation experiments on ISCAS 89 sequential benchmark circuits are also provided and discussed. The thesis also explores possible application of the ideas proposed to current embedded cores-based systems-on-chip (SOC) technologies, specifically in the context of testing memory-based synchronous digital systems.
| Identifer | oai:union.ndltd.org:uottawa.ca/oai:ruor.uottawa.ca:10393/26669 |
| Date | January 2004 |
| Creators | Jin, Chuan |
| Publisher | University of Ottawa (Canada) |
| Source Sets | Université d’Ottawa |
| Language | English |
| Detected Language | English |
| Type | Thesis |
| Format | 98 p. |
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