This dissertation proposes different methodologies, with their associated models,
to customize the architectural design of Application-Specific Networks-on-Chip
(ASNoC). Specifically, system-level evaluation models are presented and architecture
generation methodologies are built on them to allow the designer to generate the
most efficient architecture for a given NoC-based application. Our system-level
methodologies enable the designer to discover any flaws early during the design process
and to quickly investigate the effect of various design choices on the resultant NoC
cost and performance. In this dissertation, we have four main contributions.
In our first contribution, we propose power and reliability evaluation models.
The two models are proposed at the system-level to allow for a quick evaluation of
different design decisions. The power model captures the power consumption in NoC
routers and links, whereas the reliability one models the probability of the packets
being affected by on-chip noise sources.
In our second contribution, we propose a cost-efficient architecture generation
methodology for NoC based on network partitioning techniques. Our methodology
partially customizes the on-chip network architecture with respect to two cost metrics:
power and area. The partitioning technique is formulated using NoC terminology
based on the Fiduccia-Mattheyses graph partitioning algorithm. Our partitioning
scheme is compared to other partitioning techniques and is found to be the most
efficient one for NoC. We further analyze the effect of using network partitioning
on NoC power, area, and delay. From this analysis, the area reduction is proved to
be guaranteed using network partitioning. Moreover, power and delay efficiencies of
using network partitioning with NoC are formulated mathematically. Experimental
results show that the proposed methodology is an efficient way to reduce power and
area costs of NoC with respect to both standard and previous custom architecture
generation techniques.
In our third contribution, we propose a multi-objective Genetic Algorithm
(GA)-based optimization methodology for NoC full-custom architectures. For any
application, the designer could control the optimization process through different
optimization weight factors. Our methodology is evaluated by applying it to different
NoC benchmark applications, as case studies. Results show that the architectures
generated by our methodology outperform those generated by other techniques with
respect to power, area, delay, reliability, and the combination of the four metrics.
Finally, the running time of our methodology is an order of magnitude faster than
that of previous architecture optimization techniques.
In our fourth contribution, we propose a multi-objective GA-based methodology
to optimize the use of standard architectures, which were previously presented in
computer network, with NoC. Our methodology combines the best selection of NoC
standard architecture and the optimum mapping of application cores onto that
architecture. The methodology is further used to carry out an application-specific
mapping-oriented evaluation of different NoC standard architectures. Experimental
results show that the mapping achieved by our methodology outperforms those
generated by previous mapping techniques with respect to power, area, delay,
reliability, and the combination of the four metrics.
This research work aims at quickly validating various design decisions by
proposing system-level power and reliability evaluation models. Moreover, in this
dissertation, we present three application-specific methodologies to customize the
three main categories of architectures that are currently used in implementing on-chip
networks; namely, semi-custom, full-custom, and standard architectures, respectively.
Our methodologies consider different NoC metrics: power, area, delay, and reliability,
simultaneously. We believe that our proposed methodologies bridge an open gap in
NoC research by matching the on-chip network architecture to the characteristics and
the rapidly growing requirements of modern NoC applications. / Graduate
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/3631 |
| Date | 19 October 2011 |
| Creators | Morgan, Ahmed Abdel Fattah Hassan |
| Contributors | Gebali, Fayez |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Rights | Available to the World Wide Web |
Page generated in 0.0031 seconds