Modern processors aim to achieve ILP by utilizing numerous functional units, large onchip structures and wider issue windows. This leads to extremely complex designs, which
in turn adversely affect clock rate and energy efficiency. Hence, clustered processors have
been introduced as an alternative, which allow high levels of ILP while maintaining a
desirable clock rate and manageable power consumption. Nonetheless, clustering has its
drawbacks. In this work we discuss the two types of clustering-induced delays caused by
limited intra-cluster issue bandwidth and inter-cluster communication latencies. We use
simulation results to show that the stalls caused by inter-cluster communication delays
are the dominant factor impeding the performance of clustered processors. We also
illustrate that microarchitectures become more energy efficient as the number of clusters
grows. We study branch misprediction as a source of energy loss and examine how
pipeline gating can alleviate this problem in centralized and distributed processors.
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/586 |
| Date | 10 April 2008 |
| Creators | Zarrabi, Sepehr |
| Contributors | Baniasadi, Amirali |
| Source Sets | University of Victoria |
| Detected Language | English |
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