This dissertation encompasses primarily design for testability (DFT) problems of concurrent checking and structural off-line Built-In Self-Test. We present a new DFT method, which employs cyclic code checking as a medium to combine the concurrent checking and signature analysis in a built-in fashion.
It uses bit-sliced linear feedback shift registers (LFSRs) or linear cellular automata registers (LCARs) as the implementation mechanism. A circuit under test designed in this method supports both on-line and off-line testability with shared hardware resources. It has comparable on-line error-detecting ability to the conventional error-detecting codes and without affecting the high fault coverage of off-line signature analysis. This testing scheme complies with the IEEE boundary-scan standard and is applicable to general circuitry.
Evaluations of the proposed scheme are carried out with respect to the area overhead, performance and testing time, design complexity, pin count, and fault coverage.
The concatenation properties of LCARs are introduced and recent developments
in related issues are reviewed. Finally, a new area estimation method for circuit
design is presented to ease silicon cost measurement / Graduate
| Identifer | oai:union.ndltd.org:uvic.ca/oai:dspace.library.uvic.ca:1828/9607 |
| Date | 05 July 2018 |
| Creators | Sun, Xiaoling |
| Contributors | Serra, Micaela |
| Source Sets | University of Victoria |
| Language | English, English |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | Available to the World Wide Web |
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