Li Cheng. / Thesis submitted in: November 2002. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 57-61). / Abstracts in English and Chinese. / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- The Evolution of Ring Network Technologies --- p.1 / Chapter 1.1.1 --- Token Ring Technology --- p.1 / Chapter 1.1.2 --- Resilient Packet Ring Technology --- p.4 / Chapter 1.2 --- Optimal Routing --- p.7 / Chapter 1.3 --- Fairness --- p.8 / Chapter 1.4 --- Outline of Thesis --- p.10 / Chapter CHAPTER 2 --- OPTIMAL ROUTING --- p.11 / Chapter 2.1 --- Throughput Analysis --- p.11 / Chapter 2.2 --- Numerical Results --- p.13 / Chapter CHAPTER 3 --- OPTIMAL FAIR ROUTING --- p.19 / Chapter 3.1 --- Overview --- p.19 / Chapter 3.2 --- Max-min Fair Allocation --- p.19 / Chapter 3.3 --- Proportionally Fair Allocation --- p.32 / Chapter 3.4 --- Numerical Results --- p.33 / Chapter CHAPTER 4 --- TRADEOFF ANALYSIS --- p.40 / Chapter 4.1 --- Tradeoff between Throughput and Max-min Fairness --- p.40 / Chapter 4.2 --- Numerical Results --- p.42 / Chapter 4.3 --- Tradeoff between Throughput and Utility --- p.47 / Chapter 4.4 --- Numerical Results --- p.48 / Chapter CHAPTER 5 --- CONCLUSION --- p.54 / Chapter 5.1 --- Summary --- p.54 / Chapter 5.2 --- Discussion and Future Work --- p.55 / BIBLIOGRAPHY --- p.57

In the past few years Wireless Mesh Networks (WMNs) have developed as a promising technology to provide flexible and low-cost broadband network services. The Expected Transmission Count (ETX) routing metric has been put forward recently as an advanced routing metric to provide high QoS for static WMNs. Most previous research in this area suggests that ETX outperforms other routing metrics in throughput and efficiency. However, it has been determined that ETX is not immune to load sensitivity and route oscillations in a single radio environment. Route oscillations refer to the situation where packet transmission switches between two or more routes due to congestion. This has the effect of degrading performance of the network, as the routing protocol may select a non optimal path. In this thesis we avoided the route oscillation problem by forcing data transmission on fixed routes. This can be implemented in the AODV (Ad hoc On-demand Distance Vector) protocol by disabling both error messages and periodic updating messages (the HELLO scheme). However, a critical factor for our approach is that ETX must determine a high quality initial route in AODV. This thesis investigates whether the ETX metric improves initial route selection in AODV compared to the HOPS metric in two representative client-server applications: the Traffic Control Network (TCN) and the Video Stream (VS) network. We evaluate the ETX and HOPS metrics in a range of scenarios which possess different link qualities and different traffic loads. We find the ETX metric greatly improves initial route selection in AODV compared to the HOPS in the network in which only single flow exists. For networks in which there are multiple simultaneous flows, ETX behaves similar to HOPS in initial route selection. Based on these results, we find the solution of route stabilization to route oscillations in the context of ETX is only useful in the single flow case. To address this problem, we propose a modified solution of repeatedly broadcasting RREQ (Route Request) packets. Simulation results show that our modified solution allows ETX to be useful in the initial route selection in both single flow and multiple simultaneous flows cases.

<p>The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures.</p><p>This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply.</p><p>It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control.</p> / Report code: LiU-TEK-LIC-2006:36.

Ad Hoc networks are multi-hop wireless networks consisting of mobile hosts. They do not have any pre-existing network infrastructure and are characterized by constantly changing topology, limited battery power and bandwidth. Typical applications of such networks are battlefield networks, medical relief during natural calamities or disasters, conference room networking, and intra-vehicular communications. Routing packets in an ad-hoc network is a challenge because of the mobile nature of the nodes and the constantly changing topology. In ad hoc networks, each mobile node functions as a router, forwarding packets, establishing routes and helping each other in maintaining the network. A novel scalable routing protocol SLURP (Scalable Location Updated-based Routing Protocol) addresses these issues of ad hoc networks routing. The protocol is based on a location management strategy, which keeps the routing overhead to a minimum. In this thesis we compare the protocol against an existing set of multi-hop ad hoc network routing protocols that cover a range of design choices: DSDV, TORA, DSR, and AODV. We implemented SLURP in the network simulator ns-2, with the necessary wireless extensions. Experiments were run to simulate changes in network topology, number of active sources, link connectivity, and speed of motion. The difference in performance and scalability are illustrated. / Graduation date: 2003

Thesis (M.S.E.C.E)--University of Delaware, 2006. / Principal faculty advisor: Leonard J. Cimini, Jr., Electrical and Computer Engineering. Includes bibliographical references.

Thesis (MS)--Montana State University--Bozeman, 2008. / Typescript. Chairperson, Graduate Committee: Jian Tang. Includes bibliographical references (leaves 53-54).

Thesis (M.S. in Computer Science)--Naval Postgraduate School, September 2003. / Thesis advisor(s): Geoffrey Xie, John Gibson. Includes bibliographical references (p. 75-76). Also available online.

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: MAC routing protocols; ad hoc networking; MANET; performance evaluation. Includes bibliographical references (p.75-76).

Thesis (M.S.)--University of South Florida, 2003. / Title from PDF of title page. Document formatted into pages; contains 62 pages. Includes bibliographical references.

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: TCP; RED; satellite; PEP; STP; performance enhancing proxy; segment caching; IP-ABR; Internet; bandwidth reservation; IP-VBR; congestion avoidance; bandwidth sharing. Includes bibliographical references (p. 98-99).