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[pt] Este trabalho descreve um processador de sinais em tempo real e o algoritmo de Bruun para o processamento da transformada rápida de Fourier. O hardware utiliza bancos de memória comutáveis entre si e processador do tipo bit-slide para atender ao requisito de tempo real. Embora projetado especificamente para executar o algoritmo de Bruun, permite qualquer tipo de processamento de sinais, sendo necessário apenas o desenvolvimento de software. / [en] This work describes a real time signal processor and Bruun s algorithm for the Fast Fourier Transform. Hardware employs switching banks of memories and a bit-slice processor to achieve real time processing. The sistem was designed specifically for the Bruun s algorithm, but it allows any type of signal processing, only software development being required.

<p> In the past, analog circuits, discrete digital logic circuits or minicomputers have been used to implement the signal processing section of a sonar systems. More recently, microprocessor based logic circuit designs have produced a new breed of system design approach which gives designers the flexibility that has never been available through the use of analog or discrete logic circuits; however, due to the inherent slow speed of the metal-oxide semiconductor (MOS) logic circuits, incorporating microprocessors in the implementation of a sonar signal processor is not feasible. With the advent of bipolar Schottky large scale integrated circuit technology, the speed performance of the microprocessors have been improved considerably, and signal processor designs employing microprocessors are now feasible. </p> <p> The main objective of this work is to design, implement, and test a real-time digital sonar signal processor for processing pulsed CW signals. With design based on the use of the bit slice microprocessor, a signal processor has been constructed that has an 8 bit input, a 16 bit output. The processor is capable of detecting 16 different Doppler shifts. Laboratory generated signals are used in the testing and the experimental results show good agreement with the theory. A possible means of expanding the existing single channel signal processor into a multichannel processor has also been outlined. </p> / Thesis / Master of Engineering (MEngr)

International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / The growing complexity of missle, aircraft, and space vehicle systems, along with the advent of fly-by-wire and ultra-high performance unstable airframe technology has created an exploding demand for real time processing power. Recent VLSI developements have allowed addressing these needs in the design of a multi-processor subsystem supplying 10 MIPS and 5 MFLOPS per processor. To provide up to 70 MIPS a Digital Signal Processing subsystem may be configured with up to 7 Processors. Multiple subsystems may be employed in a data processing system to give the user virtually unlimited processing power. Within the DSP module, communication between cards is over a high speed, arbitrated Private Data bus. This prevents the saturation of the system bus with intermediate results, and allows a multiple processor configuration to make full use of each processor. Design goals for a single processor included executing number system conversions, data compression algorithms and 1st order polynomials in under 2 microseconds, and 5th order polynomials in under 4 microseconds. The processor design meets or exceeds all of these goals. Recently upgraded VLSI is available, and makes possible a performance enhancement to 11 MIPS and 9 MFLOPS per processor with reduced power consumption. Design tradeoffs and example applications are presented.

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