Background Somatic mutations accumulate in human cells throughout life. Some may have no adverse consequences, but some of them may lead to cancer. A cancer genome is typically unstable, and thus more mutations can accumulate in the DNA of cancer cells. An ongoing problem is to figure out which mutations are drivers - play a role in oncogenesis, and which are passengers - do not play a role. One way of addressing this question is through inspection of somatic mutations in DNA of cancer samples from a cohort of patients and detection of patterns that differentiate driver from passenger mutations. Results We propose QuaDMutEx an QuadMutNetEx, a method that incorporates three novel elements: a new gene set penalty that includes non-linear penalization of multiple mutations in putative sets of driver genes, an ability to adjust the method to handle slow- and fast-evolving tumors, and a computationally efficient method for finding gene sets that minimize the penalty, through a combination of heuristic Monte Carlo optimization and exact binary quadratic programming. QuaDMutNetEx is our proposed method that combines protein-protein interaction networks to the method elements of QuaDMutEx. In particular, QuaDMutEx incorporates three novel elements: a non-linear penalization of multiple mutations in putative sets of driver genes, an ability to adjust the method to handle slow- and fast-evolving tumors, and a computationally efficient method for finding gene sets that minimize the penalty. In the new method, we incorporated a new quadratic rewarding term that prefers gene solution set that is connected with respect to protein-protein interaction networks. Compared to existing methods, the proposed algorithm finds sets of putative driver genes that show higher coverage and lower excess coverage in eight sets of cancer samples coming from brain, ovarian, lung, and breast tumors. Conclusions Superior ability to improve on both coverage and excess coverage on different types of cancer shows that QuaDMutEx and QuaDMutNetEx are tools that should be part of a state-of-the-art toolbox in the driver gene discovery pipeline. It can detect genes harboring rare driver mutations that may be missed by existing methods.

<p>In new cars of today there are several electronically controlled systems that seek to aid the driver and make the journey as safe as possible. This include not only systems that directly control the vehicle such as ABS and ESP, but also systems that might make driving easier such as navigation systems, cruise control and even seat adjustments.</p><p>It is important that the effects on the driver from the use of such systems do not lead to an environment that diverts the attention of the driver from the main task, i.e. driving safely.</p><p>In this thesis a possible way of modeling the driver distractedness level due to the operation of these systems is discussed. This is done in Simulink with vehicle CAN data as inputs. An expert field test is done with 6 drivers over 18 trial runs with 31 secondary tasks on a highway. Two criteria are used to measure the distractedness, one objective based on the attributes of an element and one subjective, based on the use of the elements while driving during the trials. A lane monitoring system is evaluated and the offset from the lane center over time is used as an external criteria to the distractedness level. There is however no significant correlation between the external criteria and the subjective distractedness level.</p><p>The results of the subjective distractedness level are used in the model and possible future extensions to it are discussed.</p>

A novel gate driver design is proposed to improve the conversion efficiency of DC-DC converters. Conventional gate drivers provide a fixed gate driving strength (capability) over the entire output load range. However, it is demonstrated that to optimize the overall conversion efficiency, the driving capability of the gate driver circuit should be adjusted according to the loading condition. The proposed segmented gate driver consists of 8 parallel driver segments that can be turned on/off allowing the power consumption of the gate driver circuit to be dynamically adjusted. The post layout simulation results in high voltage TSMC 0.25µm CMOS process shows that up to 7% improvement in the efficiency can be achieved. Furthermore, in addition to efficiency improvements, a 60% reduction in the ringing and overshoot/undershoot was observed. An integrated segmented gate driver IC designed for AMSP35HV process was submitted for fabrication with the support from CMC.

A novel gate driver design is proposed to improve the conversion efficiency of DC-DC converters. Conventional gate drivers provide a fixed gate driving strength (capability) over the entire output load range. However, it is demonstrated that to optimize the overall conversion efficiency, the driving capability of the gate driver circuit should be adjusted according to the loading condition. The proposed segmented gate driver consists of 8 parallel driver segments that can be turned on/off allowing the power consumption of the gate driver circuit to be dynamically adjusted. The post layout simulation results in high voltage TSMC 0.25µm CMOS process shows that up to 7% improvement in the efficiency can be achieved. Furthermore, in addition to efficiency improvements, a 60% reduction in the ringing and overshoot/undershoot was observed. An integrated segmented gate driver IC designed for AMSP35HV process was submitted for fabrication with the support from CMC.

In new cars of today there are several electronically controlled systems that seek to aid the driver and make the journey as safe as possible. This include not only systems that directly control the vehicle such as ABS and ESP, but also systems that might make driving easier such as navigation systems, cruise control and even seat adjustments. It is important that the effects on the driver from the use of such systems do not lead to an environment that diverts the attention of the driver from the main task, i.e. driving safely. In this thesis a possible way of modeling the driver distractedness level due to the operation of these systems is discussed. This is done in Simulink with vehicle CAN data as inputs. An expert field test is done with 6 drivers over 18 trial runs with 31 secondary tasks on a highway. Two criteria are used to measure the distractedness, one objective based on the attributes of an element and one subjective, based on the use of the elements while driving during the trials. A lane monitoring system is evaluated and the offset from the lane center over time is used as an external criteria to the distractedness level. There is however no significant correlation between the external criteria and the subjective distractedness level. The results of the subjective distractedness level are used in the model and possible future extensions to it are discussed.

This research proposes the architecture of motor driver IC for the application of small BLDC motors. Both analog and digital mixed-mode techniques are employed here to design BLDC fan motor driver IC. The controlling method of this motor driver IC mainly utilizes analog approach. Besides, in order to prevent any damages on motors due to abnormal operations, digital control circuit is also involved in this IC. This motor driver IC is used in heat-sinking fan on notebooks as well as on the motors with very small impedance, so the IC is designed to be able to work in low supply voltage, and has high driving capability at the output stage. Via the feedback signal generated by the Hall sensor, it controls the motor driver IC so that the IC can supply current accordingly to stator coil. Therefore, the purpose of controlling motors is then achieved.

&amp / #728 / G Sniffing is computer-network equivalent of telephone tapping. A Sniffer is simply any software tool used for sniffing. Needs of modern networks today are much more than a sniffer can meet, because of high network traffic and load. Some efforts are shown to overcome this problem. Although successful approaches exist, problem is not completely solved. Efforts mainly includes producing faster hardware, modifying NICs (Network Interface Card), modifying kernel, or some combinations of them. Most efforts are either costly or no know-how exists. In this thesis, problem is attacked via modifying kernel and NIC with aim of transferring the data captured from the network to the application as fast as possible. Snort [1], running on Linux, is used as a case study for performance comparison with the original system. A significant amount of decrease in packet lost ratios is observed at resultant system.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1971. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Le mémoire de thèse est structuré en 3 chapitres. Le 1er chapitre présente le contexte de forte vitesse de commutation et de forte intégration en électronique de puissance, dans lequel s’inscrit cette thèse. Les fonctions et les enjeux de l’organe de commande rapprochée (« gate driver ») sont présentés. L’intégration du gate driver en technologie CMOS AMS 0.18 µm HV est présentée puis, plus particulièrement, l’intégration des fonctions optiques. Le 2e chapitre concerne l’étude de la transmission et de la modulation des charges à travers la barrière d’isolation optique. Un amplificateur en courant configurable a été dimensionné afin de pouvoir faire varier la résistance de grille. Une alimentation optique est intégrée en technologie AMS H18, comprenant une cellule PV et un convertisseur DC/DC à capacités commutées. Dans le 3e chapitre, 2 approches ont été développées pour la transmission du signal, la transmission dite en bande de base où les ordres de commande optiques sont l’image directe de la modulation en largeur d’impulsion (MLI), et la transmission dite numérique série où les changements d’état sont envoyés avec une trame haute fréquence. Un circuit de gestion logique et une horloge interne ont été conçus. La transmission numérique permet l’envoi d’information telle que la configuration de la résistance de grille. Le dimensionnement des circuits prend en compte une large plage de température de fonctionnement (-40°C à 140 °C), ainsi que les contraintes dues à l’alimentation optique (variation de la tension d’alimentation) et à l’alignement optique (variation du photo-courant généré). / The thesis dissertation is composed of 3 chapters. The 1st chapter introduces the thesis context of fast switching transients and highly integrated power electronics circuits. The functions and the issues of the close gate driver are presented. The gate driver is integrated in the AMS 0.18 µm technology with its optical functions. The second chapter deals with the transmission and modulation of the gate driver charge through the optical isolation barrier. A configurable buffer is designed in order to modulate the gate resistance value. An optical supply including a PV cell and a switched capacitors DC/DC converter is integrated. In the third chapter, two approaches are developed for the gate signal transfer. For the baseband analog transmission, the optical signal is a direct image of the pulse width modulation (PWM) signal whereas in the digital series transmission, only the commutation orders are transmitted in a high frequency frame. A logic circuit and an integrated clock are designed. The digital transmission allowed the transfer of information such as the gate resistance configuration. Large temperature range (-40°C to 140°C), optical supply constraints (supply voltage deviation) and optical alignment (photocurrent value deviation) are considered for the integrated circuits design.

This thesis describes the approach in designing and implementing a driver marking network traffic for quality of service provision. In the beginning distinct technologies usable for the driver development are discussed and compared to each other while the most suiting candidate is chosen for driver development. Next the thesis discusses the design of the driver according to specification and depicts a list of more specific requirements affecting the driver design itself. The focus point in design is the least possible impact on network traffic performance and the running system itself. In addition to the driver an application programming interface usable from user mode is designed and so the system as a whole ensures the marking of network traffic entirely. In the end the created driver architecture is described and the application programming interface is described in terms of use.