Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaf 54). Also available on the Internet.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 132-150). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph.D.)--University of Melbourne, School of Philosophy, Anthropology and Social Inquiry, 2009. / Typescript. Includes bibliographical references (p. 201-207)

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (leaves 168-172).

Thesis (M.S.)--University of Missouri-Columbia, 2004. / Typescript. Includes bibliographical references (leaf 54). Also available on the Internet.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1967. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

Thesis (Ph. D.)--Florida State University, 2006. / Advisor: Alfred Mele, Florida State University, College of Arts and Sciences, Dept. of Philosophy. Title and description from dissertation home page (viewed Sept. 20, 2006). Document formatted into pages; contains vii, 166 pages. Includes bibliographical references.

M.Sc. (Mathematics) / This dissertation describes the solution toa specific logical problem, the satisfiability problem, in a logic of games called Alternating-time Temporal Logic (ATL). Computation Tree Logic (CTL) is a discrete branching-time temporal logic for reasoning about labelled transition systems. ATL extends CTL to describe gametheoretic situations, where multiple agents together determine the evolution of the system. In particular, ATL explicitly provides for describing the abilities of coalitions of agents in such systems. Weprovide an automata-based decision procedure for ATL by translating the satisfiability problem for an ATL formula to the nonemptiness problem for an Alternating Biichi 'free Automaton. The key result that enables this translation is a oundedbranching tree model theorem for ATL, proving that a satisfiable formula is also satisfiable in a tree model of bounded branching degree. In terms of complexity, we show that satisfiability in ATL is complete for exponential time, which agrees with the corresponding complexity result for the fragment CTL. Closely related to ATL is an independently developed family of modal logics, the Coalition Logics. The presented results also provide a satisfiability procedure for Extended Coalition Logic interpreted over strongly playable coalition models. The structure of the dissertation is as follows: • Chapter 1 is an introduction to the topic, provides an overview of the results and a preview of the dissertation. • Chapter 2 presents some mathematical preliminaries regarding trees, automata, fixed points and game theory. • Chapter 3 discusses CTL and in particular an automata-based satisfiability procedure for CTL. • Chapter 4 introduces Alternating-time Temporal Logic (ATL) as a logic of games. • Chapter 5 contains the main results of the dissertation: first we prove a boundedbranching tree model property for ATL. Then the construction of the required automaton for satisfiability checking is described. • Chapter 6 relates the present work to some other logics of games, and in particular the Coalition Logics. • Chapter 7 finalises the dissertation with a conclusion and a look at some future research directions that might be pursued following the present work.

M.Sc. / This short dissertation is intended to give a brief account of the history and current state of affairs in the field of study called 'Zero-one Laws'. The probability of a property P on a class of finite relational structures is defined to be the limit of the sequence of fractions, of the n element structures that satisfy the property P, as n tends to infinity. A class of properties is said to have a Zero-One law if the above limit, which is usually called the asymptotic probability of the property with respect to the given class of finite structures, is either 0 or 1 for each property. The connection to the field of Mathematical Logic is given by the surprising fact that the class of properties definable by a first-order sentence has a Zero-One law with respect to the class of all finite relational structures of the common signature. We cover this result in more detail and discuss several further Zero- One laws for higher-order logics. In particular we will be interested in all those modal formulae which are 'almost surely' frame valid in the finite, i.e. those which have an asymptotic probability equal to 1 with respect to the class of all finite frames. Our goal is to find a purely logical characterization of these formulae by finding a set of axioms which describe such modal formulae absolutely. We devise a strategy and provide some Java programs to aid in this search for future research

With increasing data sets for processing, there is a requirement to build faster and smaller arithmetic circuits. One of the ways to improve the performance of higher order arithmetic units is to reduce the carry propagation levels. Multi-valued logic enables this by reducing the number of digits required to represent a range of numbers. Area reduction is also obtained through fewer operations and signals required to realise a function. Though theoretically multi-valued logic has these advantages, implementation of the multi-valued logic using CMOS has not been efficient. The main reason is because multi-valued logic is emulated in CMOS using binary switches. Two main approaches are followed in CMOS in implementing multi-valued logic using CMOS. Voltage mode logic, where the logic states are encoded using the node voltages suffer from low noise margins and limitation of radix due to the power supply. Current mode logic, where the branch currents are used to represent the logic levels suffer from high power consumption due to static current flow and requirement of restoration devices. The mindset of the post-CMOS approaches explored so far for multi-valued logic circuit design has been to replace the CMOS switches with their novel nano switches. Hence they too suffer from the same issues as CMOS implementation. Our value proposition is through the use of a truly multi-state device based on electron spin. Spin waves, which are a collection of electron spins of an atom enables multi-valued logic by allowing encoding information in the amplitude and phase of the wave.Another advantage of the spin wave fabric is that the computation is through wave propagation and interference which does not involve any movement of charge. This enables building low energy,smaller and faster multi-valued circuits. In this thesis, implementation of the basic building blocks of multi-valued logic using these novel spin wave based devices is shown. Building of arithmetic circuits like adders using these building blocks have also been demonstrated. To quantify the benefits of spin wave based multi-valued circuits, they are benchmarked with CMOS. For 32-bits, our projected comparisons show a 5X increased performance, 125X area improvement and 1717X power reduction for hexa-decimal spin wave based adders compared to binary CMOS. Similarly there is a 4X increase in performance of hexa-decimal SPWF multiplier compared to CMOS for 16 bits. Finally, we have implemented the I/O circuits for smooth interface between binary CMOS and multi-valued SPWF logic.