Spelling suggestions: "subject:"[een] MEMORY MANAGEMENT"" "subject:"[enn] MEMORY MANAGEMENT""
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An operational theory of relative space efficiencyBakewell, Adam January 2001 (has links)
No description available.
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Hardware support of recovery blocksFreeman, Michael January 1999 (has links)
No description available.
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Memory Usage Inference for Object-Oriented ProgramsNguyen, Huu Hai, Chin, Wei Ngan, Qin, Shengchao, Rinard, Martin C. 01 1900 (has links)
We present a type-based approach to statically derive symbolic closed-form formulae that characterize the bounds of heap memory usages of programs written in object-oriented languages. Given a program with size and alias annotations, our inference system will compute the amount of memory required by the methods to execute successfully as well as the amount of memory released when methods return. The obtained analysis results are useful for networked devices with limited computational resources as well as embedded software. / Singapore-MIT Alliance (SMA)
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Integration of Memory Subsystem with Microprocessor Supporting On-Chip Real Time Trace CompressionLai, Chun-hung 06 September 2007 (has links)
In this thesis, we integrate the memory subsystem, including cache and MMU¡]Memory Management Unit¡^ with the embedded 32 bits microprocessor SYS32TM-II to support the virtual memory mechanism of the operating system and make memory management effectively among multi-processes in the system. To provide the virtual to physical address translation with MMU and to improve the system performance with cache. We reuse the memory subsystem of the LEON2 SoC platform and design the communication interface to coordinate the processor core SYS32TM-II with the LEON2 memory subsystem, and modify the LEON2 memory subsystem to compatible with SYS32TM-II.
After the integration of memory subsystem, a reusing cache for program address trace compression in real time is proposed. The advantage is that reusing cache with minor hardware modification can not only save the hardware compressor overhead but also obtain a high compression ratio. Experimental results show that the proposed approach causes few hardware area overhead but achieves approximately 90% compression ratio at real-time.
Therefore, this thesis is the memory subsystem with parameterized design and with the ability to support system debugging. The role of the memory subsystem is not only to improve the system performance and to provide the hardware support requiring by the operating system, with minor modification, the memory susbsystem can also capture the dynamic program execution trace in parallel with microprocessor. The address trace compression mechanism will not effect the program execution and capable to compress at real-time.
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Dynamic cache-line sizes /Van Vleet, Taylor, January 2000 (has links)
Thesis (Ph. D.)--University of Washington, 2000. / Vita. Includes bibliographical references (leaves 128-131).
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Efficient runahead execution processorsMutlu, Onur 28 August 2008 (has links)
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Enhancing memory controllers to improve DRAM power and performanceHur, Ibrahim 28 August 2008 (has links)
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Prefetch mechanisms by application memory access patternAgaram, Kartik Kandadai 28 August 2008 (has links)
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Adaptive caching for high-performance memory systemsQureshi, Moinuddin Khalil Ahmed, 1978- 28 August 2008 (has links)
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Prefetch mechanisms by application memory access patternAgaram, Kartik Kandadai 16 August 2011 (has links)
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