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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

Scalability of the locator identity split mapping infrastructure to support end-host mobility

Mungur, Utam Avinash Einstein January 2012 (has links)
The current Internet architecture is facing serious scaling problems notably in its routing and addressing system. The TCPIIP stack uses the IP address to identify an endpoint host as well as to serve as a network topological locator. Due to the overloaded semantic of the IP address, mobility is not handled efficiently. Several Locator Identity Split proposals have been developed to decouple the actual semantic of the IP address, separating the endpoint identification and locator functions. For all Locator Identity Split protocols to work a mapping infrastructure is required. However most of the defined solutions tend to focus only on part of the problem space, and usually place end-host mobility aside. We believe that the mapping infrastructure would not scale efficiently with a large number of mobile nodes and would contribute to packet losses while the mobile nodes are moving. This thesis proposes a tiered architecture, which divides the mapping infrastructure into a core mapper and an internal mapper, such that it would scale under is a large number of mobile nodes, store and process their mapping records and provide an up-to-date mapping record. The tiered architecture is implemented using the GSE/8+8 rewriting approach. The core mapper uses a Chord DHT and the internal mapper is a hierarchy of routers with storing and rewriting capability. The tiered architecture is simulated in OMNeT++. The performance of the tiered architecture is evaluated by examining the core mapper and the internal mapper separately by simulating two real network scenarios based on the JANET topology and a University wireless network. The core mapper performance is evaluated against the Domain Name Server (DNS), and the internal mapper is evaluated using the end-host mobility provided by the Host based Identity Protocol (HIP).

Computer accessibility for colour-blind people

Jefferson, Luke Alexander January 2008 (has links)
Colour vision deficiency (CVD), often and erroneously called colour-blindness, is the collective term for a variety of abnormal physiological conditions, usually congenital, which result in fewer colour responses than normal. Despite the surprisingly high incidence of CVD (8% of men are colour vision deficient) very few commercial interfaces tackle the problem explicitly. This thesis reviews the different types of accessibility problems encountered by colour vision deficient computer users. It reports results from a questionnaire study designed to ascertain the extent to which CVD impacts computer use, the frequency at which people with CVD experience problems and the severity of these problems. This thesis demonstrates how computational models of CVD can be applied to a variety of existing software tools and interfaces to improve computer accessibility for people with CVD. Specifically, it shows how it is possible to integrate models of CVD and measures of colour difference to facilitate the selection of accessible colour schemes and to automatically map combinations of colours that colour vision deficient people find hard to discern using multi-dimensional scaling. The recolouring algorithm is evaluated using a computerised version of the standard Ishihara pseudoisochromatic plate colour vision test. The effect of applying the algorithm is to decrease (increase) error (performance) significantly for both simulated and real colour vision deficient observers so that it is comparable to the error obtained by a normal colour observer. In addition to introducing a fully automatic recolouring method, a new semi-automatic recolouring method is described along with an interface that allows the method to be delivered as an adaptive technology. The interface allows users with CVD to recolour images for their own colour vision impairment in real-time. The interface is evaluated using a perceptual image similarity task, highlighting the benefits and limits of the proposed method.

Towards mobile multi-display environments : a design exploration using projection-screen devices

Cauchard, Jessica Rebecca January 2013 (has links)
Thanks to miniaturization of display technologies, the recent years have seen the emergence of a new generation of mobile devices containing multiple displays. They are identified as Mobile Multi-Display Environments (MMDEs), building on previous work in the field of Multi-Display Environments. This doctoral work presents the first exploration and classification of this research space. In particular, I identify the case of projection-screen MMDEs, mobile devices containing both projection and screen technologies. The dissertation address the following thesis: Providing re-configurability of displays' relative placements in the heterogeneous MMDE and providing interaction using kinaesthetic cues and spatial memory, users can manage complex and highly cognitively charged tasks as well as complex information management across multiple displays. To support this thesis, the dissertation answers research questions around the possibility of synchronous use of the displays given their inherent technological and physical disparities; the optimal relative positioning of the displays; the use of the mobile-projection unit as a secondary display and the projection spaces available around the user. The contributions of this work are multiple, the main contributions are: case studies evaluating and demonstrating the usefulness of synchronous use of the multiple displays; design guidelines for MMDEs; novel interaction techniques and scenario of use; a mathematical model of perceived depth in the mobile environment; and a series of prototypes and experiments that have been designed to support this work. The dissertation shows that multiple displays can be used synchronously to improve the device's capabilities in heterogeneous projection-screen MMDEs so users can perform complex tasks across both displays. This dissertation's vision is that mobile devices with multiple displays can become as useful and as widespread as their fixed MDEs. The results presented in this dissertation further the knowledge of MMDEs.

Architecture, design and implementation of smart pixel displays

Lewis, Carl January 2013 (has links)
In the past decade, there has been significant interest in display technologies suitable for ubiquitous and ambient computing applications. Computer-augmented LED devices termed smart pixels have been gaining popularity in this research area as well as for commercial displays or architectural lighting. Compared with conventional display devices, such as LCD screens, smart pixels are flexible and unobtrusive. They may be deployed in locations where conventional displays would be infeasible and in irregular geometric arrangements, including 3D. However, up until now, smart pixels have been high complexity or limited in scalability or usability. This thesis argues for suitable requirements for a smart pixel technology which is scalable, usable, and low-complexity. A general architecture fulfilling these requirements is proposed. This architecture includes a wired network hierarchy for distributing power and data to pixels using power-line communication techniques, a location algorithm using visible-light communications and multi-view reconstruction to create an accurate 3D model of pixel positions, and a display representation suitable for allowing 2D or 3D, bitmap or vector graphic content to be rendered to a smart pixel display. An industry sponsored implementation of the architecture, Firefly, is described and used to evaluate the suitability of the proposed architecture. The major contributions of the work are the architecture itself, two novel power-line communication protocols which allow for dynamic addressing of pixels and are intended for use with high-power digital applications, and a 3D location algorithm using LEDs and cameras. The thesis concludes with a detailed summary of these contributions and proposes future work.

Symmetric active/active high availability for high-performance computing system services

Engelmann, Christian January 2008 (has links)
In order to address anticipated high failure rates, reliability, availability and serviceability have become an urgent priority for next-generation high-performance computing (HPC) systems. This thesis aims to pave the way for highly available HPC systems by focusing on their most critical components and by reinforcing them with appropriate high availability solutions. Service components, such as head and service nodes, are the "Achilles heel" of a HPC system. A failure typically results in a complete system-wide outage. This thesis targets efficient software state replication mechanisms for service component redundancy to achieve high availability as well as high performance. Its methodology relies on defining a modern theoretical foundation for providing service- level high availability, identifying availability deficiencies of HPC systems, and comparing various service-level high availability methods. This thesis showcases several developed proof-of-concept prototypes providing high availability for services running on HPC head and service nodes using the symmetric active/ active replication method, i.e., state- machine replication, to complement prior work in this area using active/standby and asymmetric active/active configurations. Presented contributions include a generic taxonomy for service high availability, an insight into availability deficiencies of HPC systems, and a unified definition of service-level high availability methods. Further contributions encompass a fully functional symmetric active/active high availability prototype for a HPC job and resource management service that does not require modification of service, a fully functional symmetric active/active high availability prototype for a HPC parallel file system metadata service that offers high performance, and two preliminary prototypes for a transparent symmetric active/active replication software framework for client-service and dependent service scenarios that hide the replication infrastructure from clients and services. Assuming a mean-time to failure of 5,000 hours for a head or service node, all presented prototypes improve service availability from 99.285% to 99.995% in a two-node system, and to 99.99996% with three nodes.

The relationship between physics and computer science

Lambert, James Alexander January 2011 (has links)
This dissertation explores the relevance of computer science to physics. Beginning with a thorough technical analysis of the concept of information and theoretical computer science I distinguish between computation simpliciter and the narrower notion of digital computation which I define as symbol manipulation. I develop a detailed account of what it means to say a physical system implements, or carries out, a computation. I discuss the difference between analogue and digital computation and conclude it is a false dichotomy. A new category of device known as an experimental computer is proposed and distinguished from an analogue computer. I critique Geroch and Hartle's desideratum that all scientific theories be computable and I finish by looking at several attempts to define 'complexity' in computational terms.

A novel self-routing reconfigurable and fault-tolerant cell array

She, Xiaoxuan January 2007 (has links)
No description available.

Design and synthesis of modern integrated filter networks : a computer-aided approach

Teplechuk, Mykhaylo A. January 2005 (has links)
No description available.

Calibration of full-waveform airborne laser scanning data for 3D object segmentation

Abed, Fanar Mansour Abed January 2012 (has links)
Airborne Laser Scanning (ALS) is a fully commercial technology, which has seen rapid uptake from the photogrammetry and remote sensing community to classify surface features and enhance automatic object recognition and extraction processes. 3D object segmentation is considered as one of the major research topics in the field of laser scanning for feature recognition and object extraction applications. The demand for automatic segmentation has significantly increased with the emergence of full-waveform (FWF) ALS, which potentially offers an unlimited number of return echoes. FWF has shown potential to improve available segmentation and classification techniques through exploiting the additional physical observables which are provided alongside the standard geometric information. However, use of the FWF additional information is not recommended without prior radiometric calibration, taking into consideration all the parameters affecting the backscattered energy. The main focus of this research is to calibrate the additional information from FWF to develop the potential of point clouds for segmentation algorithms. Echo amplitude normalisation as a function of local incidence angle was identified as a particularly critical aspect, and a novel echo amplitude normalisation approach, termed the Robust Surface Normal (RSN) method, has been developed. Following the radar equation, a comprehensive radiometric calibration routine is introduced to account for all variables affecting the backscattered laser signal. Thereafter, a segmentation algorithm is developed, which utilises the raw 3D point clouds to estimate the normal for individual echoes based on the RSN method. The segmentation criterion is selected as the normal vector augmented by the calibrated backscatter signals. The developed segmentation routine aims to fully integrate FWF data to improve feature recognition and 3D object segmentation applications. The routine was tested over various feature types from two datasets with different properties to assess its potential. The results are compared to those delivered through utilizing only geometric information, without the additional FWF radiometric information, to assess performance over existing methods. The results approved the potential of the FWF additional observables to improve segmentation algorithms. The new approach was validated against manual segmentation results, revealing a successful automatic implementation and achieving an accuracy of 82%.

Automated synthesis of delay-insensitive circuits

Sayle, Roger Anthony January 1996 (has links)
The technological trend towards VLSI circuits built from increasing numbers of transistors continues to challenge the ingenuity of both designers and engineers. The use of asynchronous design techniques presents a method for taming the complexity of large concurrent VLSI system design and offers a number of attractive advantages over conventional design styles. In this thesis, we concentrate on the useful class of delay insensitive asynchronous circuits. These have the property that their correct operation is independent of the speed of the individual elements and the delays in the connecting wires. Traditionally, asynchronous circuits are considered much harder to design than their synchronous equivalents due to their inherent nondeterminism. The use of automated formal methods for generating such circuits shields the designer from this complexity. This allows the designer to abstract away from implementation issues and reason about the system behaviour in terms of concurrent processes or high level programs. Because each step of the compilation process can be shown to be sound, the resulting circuits are correct-by-construction. This thesis presents a compilation methodology for designing delay insensitive VLSI systems from behavioural specifications. The synthesis method makes use of a graph-based representation of the circuit's behaviour. Optimization of the global behaviour, by graph transformation, enables the generation of more efficient circuits than those produced by previous asynchronous circuit compilers based on syntax-directed translation. The resulting circuits are further improved by semantics-preserving circuit transformations. A compiler has been constructed that automatically performs the translation and transformation.

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