- About
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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
Search results
Showing 771 to 780 of 10626 (0.054 seconds)| 771 |
Practical unification-based parsing of Natural LanguageCarroll, John Andrew January 1993 (has links)
No description available.
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| 772 |
Language implementation in a portable operating systemEvans, R. D. January 1981 (has links)
No description available.
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| 773 |
Programming in temporal logicHale, Roger William Stephen January 1988 (has links)
No description available.
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| 774 |
An object based architecture for software development environmentsBarman, Harry Justin January 1989 (has links)
No description available.
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| 775 |
Weak sharp minima and penalty functions in mathematical programmingFerris, Michael Charles January 1988 (has links)
No description available.
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| 776 |
Distributed object management in a non-small graph of autonomous networks with few failuresDickman, Peter William January 1991 (has links)
No description available.
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| 777 |
A knowledge representation approach to information systems analysis and modellingIp, Saimond January 1992 (has links)
No description available.
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| 778 |
Reasoning about the function and timing of integrated circuits with Prolog and temporal logicLeeser, Miriam Ellen January 1987 (has links)
The structure of circuits is specified with Prolog; their function and timing behaviour is specified with interval temporal logic. These structural and behavioural specifications are used to formally verify the functionality of circuit elements as well as their timing characteristics. A circuit is verified by deriving its behaviour from the behaviour of its components. The derived results can be abstracted to functional descriptions with timing constraints. The functional descriptions can then be used in proofs of more complex hardware circuits. Verification is done hierarchically, with transistors as primitive elements. Transistors are modeled as switch-level devices with delay. In order to model delay, the direction of signal flow through each transistor must be assigned. This is done automatically by a set of Prolog routines which also determine the inputs and outputs of each circuit component. Interval temporal logic descriptions are expressed in Prolog and manipulated using PALM: Prolog Assistant for Logic Manipulation. With PALM, the user specifies rewrite rules and uses these rules to manipulate logical terms. In the case of reasoning about circuits, PALM is used to manipulate the temporal logic descriptions of the components to derive a temporal logic description of the circuit. These techniques are demonstrated by applying them to several commonly used complementary metal oxide semiconductor (CMOS) structures. Examples include a fully complementary dynamic latch and a 1-bit adder. Both these circuits are implemented with transistors and exploit 2-phase clocking and charge sharing. The 1-bit adder is a sophisticated full adder implemented with a dynamic CMOS design style. The derived timing and functional behaviour of the 1-bit adder is abstracted to a purely functional behaviour which can be used to derive the behaviour of an arbitrary n-bit adder.
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| 779 |
Implementation and programming techniques for functional languagesWray, S. C. January 1986 (has links)
No description available.
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| 780 |
A parallel architecture for storage and retrieval of spatial dataWiegnad, Timothy Frank January 1991 (has links)
No description available.
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