To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event. The Ambipolar-Diffusion-With-Cutoff (ADC) model was extended in this work to model charge sharing, thus allowing accurate charge estimation by EDA tools An Single Event Transient (SET) pulse width estimation methodology was developed to model the Standard Cells response to the soft error. Combining these models along with circuit masking probabilities, the circuit soft-error cross-section is estimated. These soft error models are then integrated into an automatic standard cell placement tool based on Quadratic Optimization. Results show the impact of Physical Synthesis electrical correction techniques, such as Buffering, Gate Cloning and Gate Sizing, to the circuit soft error cross-section. Furthermore, an algorithm to reduce the circuit soft error cross-section by optimizing the Tap Cell placement was also developed and demonstrated. Results from this thesis provide key insights to control the circuit soft error cross-section during the Physical Synthesis design flow for integrated circuits at the most advanced technology nodes.

Finite precision error in digital signal processing creates a threshold of quality of the processed signal. It is very important to agree on the outcome while paying in terms of power and performance. This project deals with the design and implementation of digital filters FIR and IIR, which is further utilized by a measurement system in order to correctly measure different parameters. Compared to analog filters, these digital filters have more precise and accurate results along with the flexibility of expected hardware and environmental changes. The error is exposed and the filters are implemented to meet the requirements of a measurement system using finite precision arithmetic and the results are also verified through MATLAB. Moreover with the help of simulations, a comparison between FIR and IIR digital filters have been presented. / <p>Passed</p> / Digital filters and FPGA

<p> Mobile Ad-hoc Network (MANET) is a group of individual mobile nodes that exhibit mobility, which results in network congestion. The nodes in MANET are continuously moving with change in network topology that results in significant network congestion. Transmission Control Protocol (TCP) is the most popular connection oriented transport layer protocol used today. The TCP when applied over MANET faces challenges, such as congestion and non-congestion losses. We are concentrating to distinguish between these losses and overcome the non-congestion losses.</p><p> The current project presents results on the performance evaluation of various TCP implementations, as measured in terms of the following parameters: end-to-end delay; throughput; network overhead; and packet delivery ratio. Simulations of applying the various TCP schemes over MANET have been performed using the Network Simulator (NS2), and simulation results including comparisons between the different TCP schemes are presented.</p>

<p> Max-plus algebra is a suitable algebraic setting to model discrete event systems involving synchronization and delay phenomena which are often found in transportation networks, communications systems and manufacturing systems. One way of controlling this kind of systems consists in choosing the dates of input events in order to achieve the desired performances, e.g., to obtain output events in order to respect given dates. This kind of control is optimal, according to a just-in-time criterion, if the input-event dates are delayed as much as possible while ensuring the output events to occur before a desired reference date. This thesis presents the observer-based controller for max-plus linear systems where only estimations of system states are available for the controller, which is solved in two steps: first, an observer computes an estimation of the state by using the input and the output measurements, then, this estimated state is used to compute the state-feedback control action. It is shown that the optimal solution of this observer-based control problem leads to a greater control input than the one obtained with the output feedback strategy. Moreover, for the uncertain max-plus linear systems have varying processing time between each transition, this thesis presents robust observer-based controller towards optimizing process scheduling of a timed event systems according to the just in time criterion. Applications of the main results are illustrated in a high throughput screening system in drug discovery and a transportation network.</p>

<p> Wireless sensor networks experience an increase of attacks in networks in term of security. However, broadcast communication is an essential algorithm that provides a great benefit for large scale communications, especially in Building Automation System (BAS). Embedding the security in this area becomes the top priority for every industry. TESLA protocol is an algorithm that verifies and authenticates senders and has low overhead and a robust authentication mechanism. The appeal of TESLA motivates us to apply this protocol into a hierarchical wireless network architecture for BAS that has a high flexibility for formation networks. To combine these two architectures we implement the knowledge of zero knowledge protocol and a session key cryptography into the formation phase, and modify packets that were used in this phase to make TESLA-alpha protocol compatible with BAS.</p>

<p> Quantum-dot Cellular Automata (QCA) are proposed models of quantum computation, which are articulated in analogy to Von Neumann's conventional models of cellular automata. These models are worthy for the architecture of ultra-dense low-power and high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This project demonstrates a new design approach oriented to the implementation of binary comparators using QCA. This strategy is implemented for designing various architectures of binary comparator. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.</p>

<p> The complexity of the manufacturing process has motivated manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most well-known test techniques is called Built-In-Self-Test (BIST). A BIST Universal Asynchronous Receive/Transmit (UART) has the objectives to firstly satisfy specified testability requirements and to secondly generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. Although BIST techniques are becoming more common in industry, the additional BIST circuit that increases the hardware overhead increases design time and performance degradation is often cited as the reason for the limited use of BIST. </p><p> This project focuses on the design of a UART chip with embedded BIST architecture using Field Programmable Gate Array (FPGA) technology. The paper describes the problems of Very-Large-Scale-Integrated (VLSI) testing followed by the behavior of UART circuit using Verilog. In the implementation phase, the BIST technique will be incorporated into the UART design before the overall design is synthesized by means of reconfiguring the existing design to match testability requirements. The UART is targeted at broadband modems, base stations, cell phones and other designs. BIST is a design technique that allows a circuit to test itself. In this project, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.</p>

<p> Signal classification or automatic modulation classification is an area of research that has been studied for many years, originally motivated by military applications and in current years motivated by the development of cognitive radios. Its functions may include the surveillance of signals of interest and providing information to blind demodulation systems.</p><p> The problem of classifying Code Division Multiple Access (CDMA) signals in the presence of Additive White Gaussian Noise (AGWN) is explored using Decision Theory. Prior state-of-the-art has been limited to single channel digital signals such as MPSK and QAM, with few limited attempts to develop a CDMA classifiers. Such classifiers make use of the cyclic correlation spectrum for single user and feature-based neural network approach for multiple user CDMA. Other approaches have focused on blind detection, which could be used for classification in an indirect manner.</p><p> The discussion is focused on the development of classifiers using the average likelihood function. This approach will ensure that the development is optimal in the sense of minimizing the error in classification when compared with any other types of classification techniques. However, this approach has a challenging problem: it requires averaging over many unknown parameters and can become an intractable problem.</p><p> This research was successful in reducing some of the complexity of this problem. Starting with the definition of the probability of the code matrix and the development of the likelihood of MPSK signals, it was possible to find an analytical solution for CDMA signals with a small code length. Averaging over matrices with the lowest Total Squared Correlation (TSC) allowed simplifying the equations for higher code lengths. The resulting algorithm was tested using Receiver Operating Characteristic Curves and Accuracy versus Signal-to-Noise Ratio (SNR). The algorithm that classifies CDMA in terms of code length and number of active users was extended to different complex types of CDMA under the assumptions of full-loaded, underloaded, balanced and unbalanced CDMA, for orthogonal or quasi-orthogonal codes, and chip-level synchronization. </p>

<p> The problem of data gathering is considered in a wireless sensor network using mobile elements. In particular, we consider a case where data is produced at a particular node and it needs to be delivered to a predefined sink in a given time interval. Mobile elements in a wireless sensor network travel in a predefined path; they collect the data from the nodes and they deliver it to the sink. Each and every node must be visited by the mobile element, which must reach the sink within a given time constraint. Therefore, the goal is to plan a path for the mobile element that minimizes the total length travelled. We propose an algorithmic solution that builds node-disjoint tours that always include the sink, that cover the network and also optimize the total length travelled. We provide an Integer Linear Programming Algorithm (LPF) for the problem and propose two heuristic approaches for building the tours. We also evaluate the performance of our algorithm by comparing it to our optimal solution, also working on few alternative heuristic, commonly used in time-window vehicle routing problems, and demonstrating the superiority of our solution.</p>

<p> In this thesis, we describe a different implementation for in loop filtering method for 3D-HEVC. First we propose the use of adaptive loop filtering (ALF) technique for 3D-HEVC standard in-loop filtering. This filter uses Wiener-based method to minimize the Mean Squared Error between filtered pixel and original pixels. The performance of adaptive loop filter in picture based level is evaluated. Results show up to of 0.2 dB PSNR improvement in Luminance component for the texture and 2.1 dB for the depth. In addition, we obtain up to 0.1 dB improvement in Chrominance component for the texture view after applying this filter in picture based filtering. Moreover, a design of an in-loop filtering with Fast Bilateral Filter for 3D-HEVC standard is proposed. Bilateral filter is a filter that smoothes an image while preserving strong edges and it can remove the artifacts in an image. Performance of the bilateral filter in picture based level for 3D-HEVC is evaluated. Test model HTM- 6.2 is used to demonstrate the results. Results show up to of 20 percent of reduction in processing time of 3D-HEVC with less than affecting PSNR of the encoded 3D video using Fast Bilateral Filter.</p>