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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Networks-on-chip for multiprocessors

Lu, Ye January 2012 (has links)
It is anticipated that with further transistor dimension scaling as well as packaging innovation, the transistor budget will keep increasing in the next decade. However, as the benefits of transistor scaling decrease, little performance improvement and reduction in switching energy can be archived by the scaling. Bounded by slow memory and increased power, the performance of microprocessor reaches the point of diminishing return. The main focus of this thesis is to develop an effective on-chip communication architecture and processor architecture for next generation multiprocessor on a single hard wired silicon chip, or a programmable chip such as FPGA, allowing the physical property and performance of the architecture to scale with the ever increasing transistor budget offered by new technology node. A Networks-on-Chip (NoC) centric system design has been presented. This explores the main attraction of the scalability of NoC, which contrasts traditional multiprocessor interconnects, such as shared bus and crossbar, which are not scalable in terms of their performance and cost. In addition, a novel multithreading processor architecture has been developed with fast with fast single cycle thread scheduling that is capable of allocating the computation resources to the threads doing computational work rather than the threads waiting for data communication.
2

Parallelism and the software-hardware interface in embedded systems

Chouliaras, V. A. January 2005 (has links)
This thesis by publications addresses issues in the architecture and microarchitecture of next generation, high performance streaming Systems-on-Chip through quantifying the most important forms of parallelism in current and emerging embedded system workloads. The work consists of three major research tracks, relating to data level parallelism, thread level parallelism and the software-hardware interface which together reflect the research interests of the author as they have been formed in the last nine years. Published works confirm that parallelism at the data level is widely accepted as the most important performance leverage for the efficient execution of embedded media and telecom applications and has been exploited via a number of approaches the most efficient being vectorlSIMD architectures. A further, complementary and substantial form of parallelism exists at the thread level but this has not been researched to the same extent in the context of embedded workloads. For the efficient execution of such applications, exploitation of both forms of parallelism is of paramount importance. This calls for a new architectural approach in the software-hardware interface as its rigidity, manifested in all desktop-based and the majority of embedded CPU's, directly affects the performance ofvectorized, threaded codes. The author advocates a holistic, mature approach where parallelism is extracted via automatic means while at the same time, the traditionally rigid hardware-software interface is optimized to match the temporal and spatial behaviour of the embedded workload. This ultimate goal calls for the precise study of these forms of parallelism for a number of applications executing on theoretical models such as instruction set simulators and parallel RAM machines as well as the development of highly parametric microarchitectural frameworks to encapSUlate that functionality.
3

Investigating the Scalability of Tiled Chip Multiprocessors using Multiple Networks

Preethi, Sam January 2009 (has links)
The era of billion and more transistors on a single silicon chip has already begun and this has changed the direction of future computing towards building chip multiprocessors (CMP) systems. Nevertheless the challenges of maintaining cache coherency as well providing scalability on CMPs is still in its initial stages of development. This thesis therefore investigates the scalability of cache coherent CMP systems.
4

Integrating dynamic memory placement with adaptive load-balancing for parallel codes on NUMA multiprocessors

Slavin, Paul January 2008 (has links)
Parallel scientific programs executing in a NUMA environment are confronted with the problem of how to place their data in the system's physically separate memories so as to minimise the latency of accesses to this data made by the program's threads. Motivated by this poor performance, this thesis describes a technique by which the partition of a parallel program's workload that is created by a loadbalancing routine may be used to identify the affinities of the threads of this program for regions of the program's address space.
5

Fast local hardware processing for analysis of large databases

Cabal-Yepez, E. January 2007 (has links)
No description available.
6

Software-orientated system design for field programmable gate arrays

Self, R. P. January 2004 (has links)
No description available.
7

Inter-neuron interconnect strategies for hardware implementations of neural networks

Tuffy, Fergal January 2007 (has links)
No description available.
8

Parallel algorithms for hypergraph partitioning

Trifunovic, Aleksandar January 2006 (has links)
No description available.
9

Compilation and modelling of reconfigurable dataflow systems

Styles, Henry Edward January 2004 (has links)
No description available.
10

Hardware designs for function evaluation and LDPC coding

Lee, Dong-U. January 2004 (has links)
No description available.

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