Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved. / text

10 Gigabit Ethernet (GbE) demands faster optical sources to support high modulation rates. At the same time, the allowable margin in the 10 GbE link power budget is decreasing. This means that a 10 GbE system is unable to support as many tight bends, and it is more difficult to avoid the costly downtime that results when the allowable margin is exceeded. The recent introduction of bend-optimized (BO) multimode fiber (MMF) provides a clear solution. 850 nm vertical cavity surface emitting lasers (VCSELs) and MMFs have long been the most cost effective choice for short reach premise applications. As will be shown, the combination of BO-MMF with VCSELs is even more attractive.Historically, MMF systems operating at low bit rates of 10-100 Mbps used light-emitting diodes (LED) sources, which launch nearly equal power into every fibermode. This launch is approximated by the overfilled launch (OFL), which is still used to characterize the core diameter and numerical aperture of MMF. Unlike LEDs, VCSELs typically underfill the fiber core and are better represented by an encircled flux launch (EFL). Using OFL to evaluate a VCSEL-based MMF system could therefore produce inaccurate and misleading results. A recent study [1] characterized the macrobend loss of MMF with overfilled and restricted mode offset launch conditions. In this study, the MMFs performance with an EFL is evaluated, which is a more relevant launch condition for laser transmission. The impact of both launch conditions, OFL and EFL, on MMF performance is studied and compared.We characterize macrobend losses at small bend radii and their impact on thebandwidth for both standard 50/125 um MMF and a newly introduced BO-MMF.In addition, the 10 GbE link performance is also evaluated using the IEEE link model P802.3ae3.The simulation results illustrate that both macrobend loss and bandwidth are vital to the overall optical link performance. The 10 GbE link performance of the standard fiber deteriorates with macrobends, while the bend-optimized fiber is insensitive to the deployment conditions.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.

The master’s thesis consists of several parts. Describes the technology 10 Gbps Ethernet. Analyzer Ixia and Endace presents, especially their use for traffic analysis and stress testing the network devices. It deals with documents RFC concerning the routers and switch testing. Thesis includes the reports of tests switches and router performed by RFC 2544 and RFC 2889 documents. Part of the thesis is dedicated to COMBO FPGA cards. Documentations to the analyzers is created in this thesis and macro is on the CD for presentation of measurement results.

This master’s thesis deals with the design of six channel SD, HD and 3G HD-SDI digital video signal converter to 10-Gigabit Ethernet. In the introductory part, the conception of designed device is formulated. The theoretical background is provided in four chapters, where main standards and design rules related to digital electronics’ design are analyzed. The emphasis is placed on signal integrity at high-speed interconnects. There mostly practical examples, calculations and simulations are utilized. The design part contains thorough description of main subsystems’ design, implementation of FPGA, SDI input channels and 10-Gigabit Ethernet PHY. In the final part, the first tests and measurements of the build prototype are summarized. As an example, the comparison of signal integrity simulation to measurement is provided.