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by George Jor Chi-keung. / Bibliography: leaves 124-152 / Thesis (M.Ph.) -- Chinese University of Hong Kong, 1984

Paul Chorney. / "May 26, 1958." Issued also as a thesis, M.I.T. Dept. of Electrical Engineering, May, 1958. / Bibliography: leaf 81. / Army Signal Corps Contract DA36-039-sc-64637. Dept. of the Army Task 3-99-06-108 and Project 3-99-00-100.

Unpredictable hardware faults and software bugs lead to application crashes, incorrect computations, unavailability of internet services, data losses, malfunctioning components, and consequently financial losses or even death of people. In particular, faults in microprocessors (CPUs) and memory corruption bugs are among the major unresolved issues of today. CPU faults may result in benign crashes and, more problematically, in silent data corruptions that can lead to catastrophic consequences, silently propagating from component to component and finally shutting down the whole system. Similarly, memory corruption bugs (memory-safety vulnerabilities) may result in a benign application crash but may also be exploited by a malicious hacker to gain control over the system or leak confidential data. Both these classes of errors are notoriously hard to detect and tolerate. Usual mitigation strategy is to apply ad-hoc local patches: checksums to protect specific computations against hardware faults and bug fixes to protect programs against known vulnerabilities. This strategy is unsatisfactory since it is prone to errors, requires significant manual effort, and protects only against anticipated faults. On the other extreme, Byzantine Fault Tolerance solutions defend against all kinds of hardware and software errors, but are inadequately expensive in terms of resources and performance overhead. In this thesis, we examine and propose five techniques to protect against hardware CPU faults and software memory-corruption bugs. All these techniques are hardware-assisted: they use recent advancements in CPU designs and modern CPU extensions. Three of these techniques target hardware CPU faults and rely on specific CPU features: ∆-encoding efficiently utilizes instruction-level parallelism of modern CPUs, Elzar re-purposes Intel AVX extensions, and HAFT builds on Intel TSX instructions. The rest two target software bugs: SGXBounds detects vulnerabilities inside Intel SGX enclaves, and “MPX Explained” analyzes the recent Intel MPX extension to protect against buffer overflow bugs. Our techniques achieve three goals: transparency, practicality, and efficiency. All our systems are implemented as compiler passes which transparently harden unmodified applications against hardware faults and software bugs. They are practical since they rely on commodity CPUs and require no specialized hardware or operating system support. Finally, they are efficient because they use hardware assistance in the form of CPU extensions to lower performance overhead.

論文(哲學碩士)--香港中文大學硏究院中國語言及文學學部,1994. / 參考文獻: leaves 383-410 / 許子濱. / Chapter 第一章： --- 緒言 / Chapter 1. --- 研究主旨 --- p.001-002 / 註釋 --- p.003 / Chapter 2. --- 本文所據王逸《楚辭章句》版本述略 --- p.004-014 / 註釋 --- p.015-018 / 附圖 --- p.019-020 / Chapter 第二章： --- 王逸生平及學術考 --- p.021-063 / 註釋 --- p.064-071 / 附圖 --- p.72 / Chapter 第三章： --- 兩漢屈原論平議 --- p.073-117 / 註釋 --- p.118-126 / Chapter 第四章： --- 王逸以「忠信之篤、仁義之厚」說屈志考略 --- p.127-151 / 註釋 --- p.152-153 / Chapter 第五章： --- 「同姓無相去之義」考辨 / Chapter 一、 --- 王逸述屈原世系及官職考 --- p.154-166 / 註釋 --- p.167-170 / 附圖 --- p.171 / Chapter 二、 --- 釋「同姓」 --- p.172-192 / 註釋 --- p.193-196 / Chapter 三、 --- 「同姓無相去之義」說彙考 / Chapter 1. --- 王逸以降言《楚辭》者「同姓無相去 之義」說輯述 --- p.197-196 / 註釋 --- p.220-224 / Chapter 2. --- 駁「同姓無相去之義」說輯述 --- p.225-230 / 註釋 --- p.231 / Chapter 3. --- 當代有關屈原「同姓」問題論爭辨疑 --- p.232-254 / 註釋 --- p.255-256 / Chapter 四、 --- 「同姓無相去之義」源流考 --- p.257-308 / 註釋 --- p.309-317 / Chapter 五、 --- 「異姓有去國之義」論 --- p.318-326 / 註釋 --- p.327-329 / Chapter 六、 --- 據「同姓無相去之義」定《楚辭章句》 / 序文作者辨謬 --- p.330-334 / 註釋 --- p.335 / Chapter 第六章： --- 屈原待放及放逐考 --- p.366-354 / Chapter 1. --- 待放 / Chapter 2. --- 放逐 / Chapter 3. --- 居夷與水死 / 註釋 --- p.355-357 / 附圖 --- p.358-359 / Chapter 第七章： --- 屈原精合真人考 --- p.360-375 / 註釋 --- p.376-378 / 附圖 --- p.379 / Chapter 第八章： --- 結語 --- p.380-381 / 註釋 --- p.380-382 / 參考書目及論文目錄 --- p.383-410 / 附錄：《楚辭章句》序文作者新說駁議 --- p.411-443 / 註釋 --- p.444-453

Data streams in the form of potentially unbounded sequences of tuples arise naturally in a large variety of domains including finance markets, sensor networks, social media, and network traffic management. The increasing number of applications that require processing data streams with high throughput and low latency have promoted the development of data stream processing systems (DSPS). A DSPS processes data streams with continuous queries, which are issued once and return query results to users continuously as new tuples arrive. For stream-based applications, both the query-execution performance (in terms of, e.g., throughput and end-to-end latency) and the quality of produced query results (in terms of, e.g., accuracy and completeness) are important. However, a DSPS often needs to make tradeoffs between these two requirements, either because of the data imperfection within the streams, or because of the limited computation capacity of the DSPS itself. Performance versus result-quality tradeoffs caused by data imperfection are inevitable, because the quality of the incoming data is beyond the control of a DSPS, whereas tradeoffs caused by system limitations can be alleviated—even erased—by enhancing the DSPS itself. This dissertation seeks to advance the state of the art on handling the performance versus result-quality tradeoffs in data stream processing caused by the above two aspects of reasons. For tradeoffs caused by data imperfection, this dissertation focuses on the typical data-imperfection problem of stream disorder and proposes the concept of quality-driven disorder handling (QDDH). QDDH enables a DSPS to make flexible and user-configurable tradeoffs between the end-to-end latency and the query-result quality when dealing with stream disorder. Moreover, compared to existing disorder handling approaches, QDDH can significantly reduce the end-to-end latency, and at the same time provide users with desired query-result quality. In this dissertation, a generic buffer-based QDDH framework and three instantiations of the generic framework for distinct query types are presented. For tradeoffs caused by system limitations, this dissertation proposes a system-enhancement approach that combines the row-oriented and the column-oriented data layout and processing techniques in data stream processing to improve the throughput. To fully exploit the potential of such hybrid execution of continuous queries, a static, cost-based query optimizer is introduced. The optimizer works at the operator level and takes the unique property of execution plans of continuous queries—feasibility—into account.

Star-forming compact dwarf galaxies (CDGs) resemble the expected pristine conditions of the first galaxies in the Universe and are the best systems to test models on primordial galaxy formation and evolution. Here, we report on one of such CDGs, Tololo 1214-277, which presents a broad, single peaked, highly symmetric Ly alpha emission line that had evaded theoretical interpretation so far. In this paper, we reproduce for the first time these line features with two different physically motivated kinematic models: an interstellar medium composed by outflowing clumps with random motions and an homogeneous gaseous sphere undergoing solid body rotation. The multiphase model requires a clump velocity dispersion of 54.3 +/- 0.6 km s(-1) with outflows of 54.3 +/- 5.1 km s(-1), while the bulk rotation velocity is constrained to be 348(-48)(+75) km s(-1). We argue that the results from the multiphase model provide a correct interpretation of the data. In that case, the clump velocity dispersion implies a dynamical mass of 2 x 10(9) M-circle dot, 10 times its baryonic mass. If future kinematic maps of Tololo 1214-277 confirm the velocities suggested by the multiphase model, it would provide additional support to expect such kinematic state in primordial galaxies, opening the opportunity to use the models and methods presented in this paper to constrain the physics of star formation and feedback in the early generation of Ly alpha - emitting galaxies.

The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required. / Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt.

Die Dissertation erläutert, wie ein Anonymisierungsdienst zu gestalten ist, so daß er für den durchschnittlichen Internetnutzer benutzbar ist. Ein Schwerpunkt dabei war die Berücksichtigung einer möglichst holistischen Sichtweise auf das Gesamtsystem "Anonymisierungsdienst". Es geht daher um die ingenieurmäßige Berücksichtigung der vielschichtigen Anforderungen der einzelnen Interessengruppen. Einige dieser Anforderungen ergeben sich aus einem der zentralen Widersprüche: auf der einen Seite die Notwendigkeit von Datenschutz und Privatheit für den Einzelnen, auf der anderen Seite die ebenso notwendige Überwachbarkeit und Zurechenbarkeit, etwa für die Strafverfolgung. Die Dissertation beschäftigt sich mit dem Aufzeigen und Entwickeln von technischen Möglichkeiten, die zur Lösung dieses Widerspruches herangezogen werden können.

Virtualization is a mature technology in server and desktop environments where multiple systems are consolidate onto a single physical hardware platform, increasing the utilization of todays multi-core systems as well as saving resources such as energy, space and costs compared to multiple single systems. Looking at embedded environments reveals that many systems use multiple separate computing systems inside, including requirements for real-time and isolation properties. For example, modern high-comfort cars use up to a hundred embedded computing systems. Consolidating such diverse configurations promises to save resources such as energy and weight. In my work I propose a secure software architecture that allows consolidating multiple embedded software systems with timing constraints. The base of the architecture builds a microkernel-based operating system that supports a variety of different virtualization approaches through a generic interface, supporting hardware-assisted virtualization and paravirtualization as well as multiple architectures. Studying guest systems with latency constraints with regards to virtualization showed that standard techniques such as high-frequency time-slicing are not a viable approach. Generally, guest systems are a combination of best-effort and real-time work and thus form a mixed-criticality system. Further analysis showed that such systems need to export relevant internal scheduling information to the hypervisor to support multiple guests with latency constraints. I propose a mechanism to export those relevant events that is secure, flexible, has good performance and is easy to use. The thesis concludes with an evaluation covering the virtualization approach on the ARM and x86 architectures and two guest operating systems, Linux and FreeRTOS, as well as evaluating the export mechanism.