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A language-based design methodology for the design of digital electronic circuits has been developed and implemented. The methodology is suitable for the high-level synthesis of Very Large Scale Integrated (VLSI) circuits, which are specified behaviourally in an IEEE standard hardware description language, VHDL. The output is a register-transfer level specification of the same circuit, with a bound hardware structure that meets the designer's area and speed requirements. We believe that this work is the first high-level synthesis research to preserve VHDL simulation semantics. To this end, we have developed a process model based on the VHDL process statement onto which all behavioural descriptions can be mapped. The synthesis methodology is based on two major sets of transformations: behavioural transformations and control/data flow graph (CDFG) transformations. The first employs several known language compiler optimisation techniques with a goal to minimising data path and controller area, or making user-directed tradeoffs between data path and controller area for an improved speed. CDFG transformations are the workhorse of data path and control synthesis. A graph notation and algebra are developed that support efficient algebraic graph transformations. Data path and control synthesis algorithms that operate on our CDFG model, the VHDL Intermediate Graph (VIG), are presented. Examples from the High-Level Synthesis Workshop benchmark suite are synthesised and results shown. To round up the work, several problems and issues that face high level synthesis both in research and in the real world are discussed in this thesis.

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In this thesis the application of analogue charge-coupled devices (CCD's) to adaptive signal processing is considered. This research has lead to the design of several novel signal processing modules which have been evaluated here with reference to the inherent error sources in analogue CCD circuits. Error sources such as charge-transfer inefficiency and dark current integration have been evaluated in the context of specific circuit architectures and appropriate techniques for the minimisation of these effects have been advocated. The problem of drift in analogue circuits has also been examined and a particular system implementation which appears to be largely immune from this problem is described. The processors described in this thesis are all baseband systems working at clocking rates between a few hundred Hertz and about 500 kHz. The areas of application being investigated therefore include voiceband processing, high speed modems and sonar applications, including some applications in medical electronics which also fall within the operational range of these processors. Basically, two classes of CCD signal processing module are considered; open-loop and closed-loop modules. These two classes of filter may be broadly defined as processors which have fixed impulse response characteristics (open-loop) and those which employ feedback to adjust their own filter weights according to an estimate of the accuracy of the filter output (closed-loop or true adaptive processors). Two open-loop experimental modules are described: (1) a statistical analyser module which is capable of detecting pulses in noise by the use of an adaptive thresholding technique which automatically measures noise level at the system input: and (2) a module which adaptively cancels the fixed pattern noise on the output of a serial-parallel-serial CCU delay line by the use of a coherent integration technique. Both these modules illustrate the advantage of analogue CCD circuits over standard digital techniques in terms i of power consumption and speed of operation. However, they also illustrate a major problem with analogue CCU circuits which is that of d.c. stability. Under the heading of closed-loop processors two experimental CCU adaptive filters are described. One of which is based on a monolithic 64-point programmable filter (PTF) and the other based on a monolithic 256-point PTF. The main features demonstrated using these modules is the inherent correction of the errors described above when the CCD filter is in a closed-loop configuration and also the inherent d.c. stability of these systems in this configuration. Results are presented which demonstrate the predictability of these modules from theoretically ideal models and also their operation in such key applications as adaptive cancellation and line equalisation.

The demand for larger more complex systems on a single IC has shown a steady increase and to date has been met by improvements in fabrication technology. In the future it may not be possible to satisfy this demand in the same way, as it will become increasingly expensive to obtain the required process improvements. It seems likely that the demand for even larger single chip systems will continue and that the commercial success of these devices will become more heavily dependent on their yield. At the same time there is also a continuing trend towards more automated layout generation and these layouts are usually less dense than those produced using traditional hand-crafted designs. This thesis addresses the problem of maximising the yield of circuit layouts and introduces a yield improvement concept of Local Design Rules. These are integrated circuit layout rules that are used to increase a circuit's yield by making more efficient use of the circuit area. The rules define a more optimum feature size and spacing of components in relation to the surrounding layout geometry. This enables the 'unused' silicon to be reclaimed and used to enhance the circuit yield without violating the layout design rules. The type of circuit and nature of circuit layout to which local design rules can be applied to give useful yield improvement are discussed highlighting the problems in a fabrication process that can be improved by this type of layout manipulation. The impact of layout changes on the circuit performance that have been made on the suggestion of local design rules is addressed. Algorithms for the automatic application of track displacement, track width increase and contact increase local design rules are presented along with a spatial data structure suitable for efficient design rule checking of the suggested layout changes. These algorithms have been implemented and used to apply local design rules to integrated circuit layouts. Finally, several examples are presented with results from Monte Carlo yield simulations.

In particular, the Volterra and the radical basis function (RBF) expansion techniques are considered to implement the nonlinear filter structures. These approaches, however, will generate filters with very large numbers of parameters. As large filter models require significant implementation complexity, they are undesirable for practical implementations. To reduce the size of the filter, the orthogonal least squares (OLS) algorithm is considered to perform model selection. Simulations were conducted to study the effectiveness of subset models found using this algorithm, and the results indicate that this selection technique is adequate for many practical applications. The other aspect of the OLS algorithm studied is its implementation requirements. Although the OLS algorithm is very efficient, the required computational complexity is still substantial. To reduce the processing requirement, some fast OLS methods are examined. Two major applications of nonlinear filters are considered in the thesis. The first involves the use of nonlinear filters to predict time series with possesses nonlinear dynamics. To study the performance of the nonlinear predictors, simulations were conduced to compare the performance of these predictors with conventional linear predictors. The simulation results confirm that nonlinear predictors normally perform better than linear predictors. Within its study, the application of RBF predictors to time series that exhibit homogeneous nonstationarity is also considered. This type of time series possesses the same characteristic throughout the time sequence apart from local variations of mean and trend. The second application involves the use of filters for symbol-decision channel equalisation. The decision function of the optimal symbol-decision equaliser is first derived to show that it is nonlinear, and that it may be realised explicitly using a RBF filter. Analysis is then carried out to illustrate the difference between the optimum equaliser's performance and that of the conventional linear equaliser. In particular, the effects of delay order on the equaliser's decision boundaries and bit error rate (BER) performance are studied. The minimum mean square error (MMSE) optimisation criterion for training the linear equaliser is also examined to illustrate the sub-optimum nature of such a criterion. To improve the linear equaliser's performance, a method which adapts the equaliser by minimising the BER is proposed. Our results indicate that the linear equalisers performance is normally improved by using the minimum BER criterion. The decision feedback equaliser (DFE) is also examined. We propose a transformation using the feedback inputs to change the DFE problem to a feedforward equaliser problem. This unifies the treatment of the equaliser structures with and without decision feedback.

Simulation software has become an essential tool in the design and development of integrated circuits. The key to the rapid and efficient designs required in the competitive industry lies with the use of these simulators with statistical optimisation methods. This is necessary if companies are to survive in the aggressive IC marketplace. The linking of simulation and statistics not only results in rapid development times, but also in robust, highly manufacturable products. In this work an automated software system is presented where the benefits of simulation and statistical techniques can be readily made available. The efficiency of the system is increased further by utilising parallel processing techniques. Using one system built round the INMOS transputer and one using Intel 1860 processors, the time taken to obtain simulation results is greatly reduced. Two statistical methods are investigated, namely Response Surface Methodology (RSM) and Taguchi analysis. In order to illustrate how these approaches can be utilised in the field of semiconductors, part of a 1.5 μm nMOS process is optimised in relation to some specified device parameters. A comparison is made between both techniques, with good agreement being obtained. Finally devices have also been fabricated using the same experimental design as for the RSM simulation analysis. This facilitated a verification of the simulation optimisation with reality. Both simulated and fabricated devices suggested the same improved optimised conditions when compared to the existing process parameters.

Bio-medical imaging is a large umbrella term which covers a number of different imaging modalities used in healthcare today, spanning pre-clinical imaging, to diagnostic imaging and imaging to assist and plan patient treatment. This field of research is pivotal to driving advances in healthcare. This is underpinned by advances in new detector technologies which have the potential to reduce image acquisition time and dose, improving image quality and offer more accurate tools for diagnosis and treatment. Large area CMOS Active Pixel Sensors (APSs) have the potential to deliver these advances in such demanding and continuously evolving field; large imaging area, together with low noise, low cost, fast readout, high dynamic range and potential for in-pixel intelligence have made this technology an ideal candidate to displace currently used imaging technologies in this field. This thesis represents the first investigation into the capabilities of large area CMOS APSs to be used across a number of different imaging modalities in bio-medical science, spanning protein imaging to proton Computed Tomography (CT), using both ionising and non-ionising radiation sources. A novel characterisation of the detector performance has been carried out and set into context of commonly used detectors for bio-medical imaging. Considering the performance parameters assessed for this detector, in comparison with digital detectors commonly used in the clinical practise, this demonstrates how such large area sensor technology may be successfully employed in bio-medical imaging. The novel large area CMOS APS, studied in this work, is proposed as a multi- modality imaging platform for use in pre-clinical science. For the first time direct “contact print” imaging of radioactive and optical labeled biological samples on a large imaging area has been demonstrated, showing its potential application to a broad range of ionising and non-ionising imaging probes. The protein detection capability of this detector has been compared with both film emulsion and commercially available digital systems, demonstrating a higher resolution in protein detection than either film emulsion or a commonly used commercial CCD-based western blotting detection system. Also, when detection capabilities of this imaging system are compared with the state-of-the art devices for tissue autoradiography, this detector system exhibits a sensitivity comparable to that reported for its competitors, whilst offering the largest imaging area. Both these proof of concepts pave the way for large area CMOS APSs to be used as a multi- modality imaging platform in life science. The radiation hardness of a novel large area CMOS APS, designed for medical applications and hardened-by-design, is presented. The radiation damage, produced in this sensor by X-ray and proton irradiation, has been studied as function of total ionising dose and displacement damage dose. The damage contributions from ionising and non-ionising energy deposition have been separated for the proton field and proved independent from proton energy providing a further verification of the Non Ionising Energy Loss (NIEL) scaling hypothesis. The lifetime of this detector for routine use in clinical practice has been evaluated as high as 4 years when used in a typical MegaVolt- age radiotherapy environment, demonstrating how such large area sensor technology may be successfully employed in X-ray and proton based imaging applications. The feasibility of using CMOS APSs as energy-range detectors in proton CT has been demonstrated. Capability of single proton counting, together with potential of energy deposition measurements, have been demonstrated for CMOS APSs. Furthermore, experimental work, based on a simple stack of two CMOS sensors, as well as simulation work has been carried out to prove the capability of such a detection system for pro- ton tracking. Novel algorithms have been developed to perform proton tracking in a CMOS energy-range telescope designed to perform proton CT, paving the way for a new generation of imaging devices to be used in this application.

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