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In multiuser multi-antenna wireless systems, the transmission and beamforming strategies that achieve the sum rate capacity depend critically on the acquisition of perfect Channel State Information at the Transmitter (CSIT). Accordingly, a high-rate low-latency feedback link between the receiver and the transmitter is required to keep the latter accurately and instantaneously informed about the CSI. In realistic wireless systems, however, only imperfect CSIT is achievable due to pilot contamination, estimation error, limited feedback and delay, etc. As an intermediate solution, this thesis investigates novel transmission strategies suitable for various imperfect CSIT scenarios and the associated beamforming techniques to optimise the rate performance. First, we consider a two-user Multiple-Input-Single-Output (MISO) Broadcast Channel (BC) under statistical and delayed CSIT. We mainly focus on linear beamforming and power allocation designs for ergodic sum rate maximisation. The proposed designs enable higher sum rate than the conventional designs. Interestingly, we propose a novel transmission framework which makes better use of statistical and delayed CSIT and smoothly bridges between statistical CSIT-based strategies and delayed CSIT-based strategies. Second, we consider a multiuser massive MIMO system under partial and statistical CSIT. In order to tackle multiuser interference incurred by partial CSIT, a Rate-Splitting (RS) transmission strategy has been proposed recently. We generalise the idea of RS into the large-scale array. By further exploiting statistical CSIT, we propose a novel framework Hierarchical-Rate-Splitting that is particularly suited to massive MIMO systems. Third, we consider a multiuser Millimetre Wave (mmWave) system with hybrid analog/digital precoding under statistical and quantised CSIT. We leverage statistical CSIT to design digital precoder for interference mitigation while all feedback overhead is reserved for precise analog beamforming. For very limited feedback and/or very sparse channels, the proposed precoding scheme yields higher sum rate than the conventional precoding schemes under a fixed total feedback constraint. Moreover, a RS transmission strategy is introduced to further tackle the multiuser interference, enabling remarkable saving in feedback overhead compared with conventional transmission strategies. Finally, we investigate the downlink hybrid precoding for physical layer multicasting with a limited number of RF chains. We propose a low complexity algorithm to compute the analog precoder that achieves near-optimal max-min performance. Moreover, we derive a simple condition under which the hybrid precoding driven by a limited number of RF chains incurs no loss of optimality with respect to the fully digital precoding case.

Model Predictive Control (MPC) is an advanced control method that is capable of explicit performance optimization, systematic constraint handling and dealing with nonlinearities in a natural way. The necessity of solving an optimization problem at each sampling instant makes MPC a computationally demanding technique, especially when applied to fast dynamical systems. This thesis is concerned with developing efficient hardware implementations of linear and nonlinear model predictive controllers. In the first part of this thesis, a software toolchain for quick prototyping of embedded optimization algorithms on Field-Programmable Gate Arrays (FPGAs) is presented. The toolchain consists of two software tools: SPLIT and Protoip. SPLIT is capable of generating CPU and FPGA-oriented C code for embedded optimization using operator splitting methods. The generated code can be automatically deployed and tested on an embedded platform using a new release of Protoip, a software tool for quick prototyping of optimization algorithm on CPUs, FPGAs and heterogeneous platforms that incorporate both general-purpose processors and reconfigurable logic. The second part presents a framework for implementation of nonlinear model predictive control on a heterogeneous computing platform. Splitting the computational workload between a general-purpose CPU and an FPGA allows exploiting the strengths of each computational subsystem and trading off control performance against reconfigurable logic usage. A new method for scheduling sparse matrix-vector multiplication within the proposed implementation enables significant improvements in terms of memory and computational resources usage. The third part of this thesis presents an application of systematic optimization to the co-design of MPC software and computational hardware. A procedure for formulating the MPC design problem as a multi-objective optimization problem is described. Finally, two test cases including CPU and FPGA-based implementations of predictive controllers are considered.

High-Level Synthesis (HLS) tools enable an FPGA circuit developer to trade performance for productivity by mapping a high-level circuit description into hardware. However, current HLS tools have limited support for fault-tolerance and memory management. This thesis addresses these issues by using a known software technique called program slicing to construct HLS optimisation passes. These optimisation passes use program slicing to create “slice circuits” that help the primary circuit at runtime. There are three main contributions in this thesis SliceUp, RELISH, and StitchUp. SliceUp is an API that can be used to create program slicing based HLS optimisation passes. The second is RELISH, an open source HLS optimisation pass that constructs an application specific prefetcher that can hide memory latency no matter how irregular the application’s access pattern. Both a theoretical and experimental analysis is performed on RELISH, showing that speedup is bounded between 1x – 2x and with experimental results in the range 1.02x – 1.69x. Finally, StitchUp is an open source HLS optimisation pass that builds a checker circuit that ensures the correct path is taken through the original circuit in the presence of soft-errors. This saves area over traditional approaches and reduces the number of false positives required for detection.

This thesis introduces a new technique, and its associated tool SOAP, to automatically perform source-to-source optimization of numerical programs, specifically targeting the trade-off among numerical accuracy, latency, and resource usage as a high-level synthesis flow for FPGA implementations. A new intermediate representation, MIR, is introduced to carry out the abstraction and optimization of numerical programs. Equivalent structures in MIRs are efficiently discovered using methods based on formal semantics by taking into account axiomatic rules from real arithmetic, such as associativity, distributivity and others, in tandem with program equivalence rules that enable control-flow restructuring and eliminate redundant array accesses. For the first time, we bring rigorous approaches from software static analysis, specifically formal semantics and abstract interpretation, to bear on program transformation for high-level synthesis. New abstract semantics are developed to generate a computable subset of equivalent MIRs from an original MIR. Using formal semantics, three objectives are calculated for each MIR representing a pipelined numerical program: the accuracy of computation and an estimate of resource utilization in FPGA and the latency of program execution. The optimization of these objectives produces a Pareto frontier consisting of a set of equivalent MIRs. We thus go beyond existing literature by not only optimizing the precision requirements of an implementation, but changing the structure of the implementation itself. Using SOAP to optimize the structure of a variety of real world and artificially generated arithmetic expressions in single precision, we improve either their accuracy or the resource utilization by up to 60%. When applied to a suite of computational intensive numerical programs from PolyBench and Livermore Loops benchmarks, SOAP has generated circuits that enjoy up to a 12x speedup, with a simultaneous 7x increase in accuracy, at a cost of up to 4x more LUTs.

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