This thesis investigates the design of modular voltage source converters for High Voltage Direct Current (HVDC) applications. The first half of the thesis focuses on the design of existing multilevel HVDC technology. A design methodology for sizing modular converters for a given grid code specification, and with given design constraints in terms of peak sub-module voltage rating and capacitor size, is developed and used as the basis of comparing converter designs. Results show that the half-bridge MMC requires an energy storage in the region of 35 kJ/MVA in order to achieve a good balance between sub-module capacitor size, and required number of sub-modules. The design of the Hybrid MMC, which combines half- and full-bridge sub-modules in the design in order to achieve DC fault tolerance, is then investigated using the same design methodology, an advantage of which is that the optimum modulation index can be determined, rather than assumed. Results show that the highest efficiencies may be achievable if the converter is operated at a modulation index of 1.2. The power-loss and thermal properties of several converters are then analysed. The Alternate Arm Converter and over-modulating Hybrid MMC show the greatest efficiencies, though the AAC suffers from relatively high junction temperatures within its director switches. The potential of designing overload capability into MMCs, to enable them to provide system support services such as frequency response is then investigated. Results show 30% overload ratings may be achievable with only a 10% require increase in the number of sub-modules within the converter. System studies show that significant response improvements to the AC system can be made even if the converters need to be dynamically rated to prevent excessive junction temperatures being reached. The second half of this thesis focuses on a brand new multilevel thyristor-augmented structure called a power-group, which has the potential to allow voltage source converters that are tolerant to faults on both the AC and DC network to be constructed, while having efficiencies similar to those achievable with Current Source Converter (CSC) technology. Results show that this is possible while also retaining high quality current waveforms and independent control of real and reactive power. Results throughout the thesis are backed up by a combination of simulation and experimental work using a lab-scale multilevel converter that was constructed during the project.

There are numerous security challenges in cellular mobile networks, many of which originate from the Internet world. One of these challenges is to answer the problem with increasing rate of signalling messages produced by smart devices. In particular, many services in the Internet are provided through mobile applications in an unobstructed manner, such that users get an always connected feeling. These services, which usually come from instant messaging, advertising and social networking areas, impose significant signalling loads on mobile networks by frequent exchange of control data in the background. Such services and applications could be built intentionally or unintentionally, and result in denial of service attacks known as signalling attacks or storms. Negative consequences, among others, include degradations of mobile network’s services, partial or complete net- work failures, increased battery consumption for infected mobile terminals. This thesis examines the influence of signalling storms on different mobile technologies, and proposes defensive mechanisms. More specifically, using stochastic modelling techniques, this thesis first presents a model of the vulnerability in a single 3G UMTS mobile terminal, and studies the influence of the system’s internal parameters on stability under a signalling storm. Further on, it presents a queueing network model of the radio access part of 3G UMTS and examines the effect of the radio resource control (RRC) inactivity timers. In presence of an attack, the proposed dynamic setting of the timers manage to lower the signalling load in the network and to increase the threshold above which a network failure could happen. Further on, the network model is upgraded into a more generic and detailed model, represent different generations of mobile technologies. It is than used to compare technologies with dedicated and shared organisation of resource allocation, referred to as traditional and contemporary networks, using performance metrics such as: signalling and communication delay, blocking probability, signalling load on the network’s nodes, bandwidth holding time, etc. Finally, based on the carried analysis, two mechanisms are proposed for detection of storms in real time, based on counting of same-type bandwidth allocations, and usage of allocated bandwidth. The mechanisms are evaluated using discrete event simulation in 3G UMTS, and experiments are done combining the detectors with a simple attack mitigation approach.

Electromyogram (EMG), the recording of the electrical impulses of the muscles, is a rich source of information, which can facilitate such an insight into our muscles and especially their activation and fatigue level. Muscle fatigue has been shown to be one of the most important biofeedback parameters of EMG in rehabilitation, ergonomics and training, by using measured results from the body to change the way we behave, improve our performance and achieve better compliance to rehabilitation. This thesis addresses the challenge of reliably and efficiently estimating a muscle’s fatigue state though monitoring surface EMG signals, with the use of low power integrated circuits. CMOS technology facilitates localised real-time processing to achieve complete miniaturisation, resulting in an information driven system rather that conventionally data driven system. Thus, reducing requirements on data transmission, saving power and increasing the degree of freedom for the user. Several EMG properties progressively change during muscle fatigue and can be quantified in the time and frequency domains using different processing techniques. CMOS technology allows to significantly reduce the power and size of the developed EMG processing technology. Firstly, a CMOS system is presented, capable of measuring the instantaneous Median Frequency (iMDF) of the EMG signal, which is considered the golden standard for muscle fatigue assessment. Continuing, a novel bit-stream cross-correlator design that greatly simplifies the sEMG signal without any loss of information is presented for the estimation of the EMG conduction velocity, which is associated with the physiological changes of the muscle during fatigue. Furthermore, a new metric similar to iMDF is introduced, combining the advantages of the bit-stream approach that can accurately track the spectral compression of the sEMG during fatigue with one bit representation. Lastly, a complete muscle fatigue monitoring System-on-Chip (SoC) is presented, offering complete insight into the underlying mechanisms and physiological changes during muscle fatigue through sEMG analysis while operating under both static and dynamic contractions. The proposed approach is scalable, as several muscle fatigue monitoring SoCs can operate in parallel and periodically relay key information about the muscle, thus reducing data transmission costs and bandwidth requirements. Finally, a succession of wearable EMG devices are presented, introducing the use of custom Application Specific Integrated Circuits in wearable electronics for unsupervised muscle fatigue monitoring. The wearable nodes are wireless while user ergonomics, power and weight were the primary design considerations.

Energy harvesting is one of the key technologies for the realization of autonomous sensing. The aim of this thesis is to develop low-frequency broadband rotational energy harvesting solutions for self-powered sensing. As an example of rotational energy harvesting, an airflow energy harvester using a miniaturized turbine and piezoelectric transduction was first introduced. Rotation was converted from airflow by the turbine, and a piezoelectric beam was actuated by the turbine rotor using magnetic plucking. Issues, including high cut-in speed and low output power at high rotational frequencies, were discovered. In order to decrease the cut-in speed, a self-regulating mechanism was proposed and integrated. The magnetic plucking strength can be passively adjusted according to the rotational speed. This self-regulating harvester exhibited a lower cut-in speed. In order to understand the limited performance at high rotational frequencies and to optimize the design, a theoretical model was built. Different arrangements were investigated, showing that this harvester is ideal to operate at low excitation frequency far below the piezoelectric beam's resonant frequency. Bistable behaviour was also employed and studied to enhance the energy harvesting capability over a wide bandwidth at low frequency. Then, a complete self-powered condition monitoring system, including a bistable frequency up-converting harvester, a power management circuit and a wireless sensor node, was studied and developed to implement the concept of self-powered sensing. Finally, a fundamental study was conducted for three types of rotational energy harvesters, including electromagnetic, piezoelectric resonant, and piezoelectric non-resonant harvesters. Scaling laws for each type were established to study harvesters' performance for different operating frequencies and device dimensions. This study provides a guideline for selection and design of rotational energy harvesters with specific requirements of device dimension and operating frequency.

This thesis proposes novel analytical models for assessing the role and the value of various flexibility resources in the future low-carbon systems with high penetration of renewable energy resources. A novel stochastic scheduling model is developed, which optimises system operation by simultaneously scheduling energy production, standing/spinning reserves and inertia-dependent frequency regulation in light of uncertainties associated with wind energy production and thermal generation outages. The proposed model is shown to be particularly suitable for analysing the value of flexibility. Following this, the thesis presents an assessment of the value that energy storage may deliver to the owner in the application to energy and ancillary service markets. The results suggest that the value of energy storage is mainly driven by the temporal arbitrage opportunities created by volatility in energy prices. The value of energy storage is shown to be site-specific when there are active network constraints. A novel methodology is then proposed and applied to assess the role and the value of frequency regulation support (synthetic inertia (SI) and primary frequency response (PRF)) from wind plants (WPs). The results suggest the SI could effectively reduce the system operation cost in the system, especially with high penetration of wind generation. The analysis also demonstrates the value for WPs in providing PFR is system-specified. Combined provision of SI and PFR is required, in the case that there exists severe recovery effect associated with SI provision. This thesis also proposes a novel demand side response model (DSRM), which models and controls the recovery period during and after frequency regulation provision and thus optimally allocates multiple frequency services. The results attest the value of the DSRM compared with alternative approaches for demand response schemes. Moreover, this thesis quantifies the implications of electric vehicle deployment, heat pumps, industrial and commercial and dynamic time-of-use tariffs for the carbon emissions and renewable integration cost of the broader GB electricity system. Finally, this thesis investigates the value of enhanced flexibility from conventional plants. It has been shown that the value increases with penetration of RES; however, different systems may require different types of enhanced flexibility features. Moreover, different system scheduling methods, risk attitudes, frequency response requirements and carbon prices could significantly change the value of flexibility.

The growing need to obtain large amounts of genomic data for various applications has motivated efforts to drop the cost and time of DNA sequencing and assembly. At the forefront of these, semiconductor based sequencing using Ion-Sensitive Field Effect Transistors (ISFETs) shows great promise. This thesis explores methods to improve ISFET sensor performance using novel front-end topologies in CMOS in addition to introducing new real-time parallel processing methods to allow more robust and rapid DNA sequencing and assembly in hardware. The novel front-ends utilise capacitive feedback. By doing so, all the existing challenges in ISFET sensors such as trapped charge, sensitivity loss and drift can be solved. Three different topologies ( two-stage, single-stage and 3-Transistor) are discussed and compared. The single stage front-end is also found to be the most suitable structure for implementing large arrays of sensors. A novel automatic calibration system is designed to compensate for the gain mismatches in the sensor array, which monitors the amplitude of high frequency sine waves superimposed on the chemical signals. A trade-off between speed and resolution is resolved by adding additional lowpass filters in the loop. Following this, a full system comprising a $32\times32$ ISFET array, an automatic gain calibration system, control logics and SPI is implemented. The correlated double sampling system which eliminates the offset problem is realized in digital domain. An SPI protocol is used to send off the digitalised data to off-chip memory, as well as the data retrieval. The test results indicate a good performance in offset cancellation and gain consistency. Finally a real-time DNA fragment comparison system is implemented in the FPGA for DNA assembly. To handle with the incomplete data set during the sequencing time, a novel hybrid comparison algorithm is proposed. The original all-against-all comparison step in the OLC method is firstly decomposed into successive window-against-window comparison phases, and then dynamic programming is grafted on the exact comparison to achieve high speed but error-tolerant computation. Hierarchical implementation in FPGA is represented where processing units are paralleled and controlled by one global controller. The validation of the proposed system is proven by the assembly of three real DNA sets even with deliberate errors introduced.

Truly Wearable EEG (WEEG) can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting, miniature and wearable devices that can be easily worn by patients will result in more EEG data being collected for extended monitoring periods. This thesis presents three new fabricated systems, in the form of Application Specific Integrated Circuits (ASICs), to aid the diagnosis of epilepsy and sleep disorders by detecting specific clinically important EEG events on the sensor node, while discarding background activity. The power consumption of the WEEG monitoring device incorporating these systems can be reduced since the transmitter, which is the dominating element in terms of power consumption, will only become active based on the output of these systems. Candidate interictal activity is identified by the developed analog-based interictal spike selection system-on-chip (SoC), using an approximation of the Continuous Wavelet Transform (CWT), as a bandpass filter, and thresholding. The spike selection SoC is fabricated in a 0.35 μm CMOS process and consumes 950 nW. Experimental results reveal that the SoC is able to identify 87% of interictal spikes correctly while only transmitting 45% of the data. Sections of EEG data containing likely ictal activity are detected by an analog seizure selection SoC using the low complexity line length feature. This SoC is fabricated in a 0.18 μm CMOS technology and consumes 1.14 μW. Based on experimental results, the fabricated SoC is able to correctly detect 83% of seizure episodes while transmitting 52% of the overall EEG data. A single-channel analog-based sleep spindle detection SoC is developed to aid the diagnosis of sleep disorders by detecting sleep spindles, which are characteristic events of sleep. The system identifies spindle events by monitoring abrupt changes in the input EEG. An approximation of the median frequency calculation, incorporated as part of the system, allows for non-spindle activity incorrectly identified by the system as sleep spindles to be discarded. The sleep spindle detection SoC is fabricated in a 0.18 μm CMOS technology, consuming only 515 nW. The SoC achieves a sensitivity and specificity of 71.5% and 98% respectively.

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