No description available.

One of the many important algorithmic techniques in digital signal processing is real-time digital filtering. Modular sliced structures for digital filters have been proposed before, but the nature of implementation has been mainly constrained to non-recursive second order digital filters with positive values of coefficients. The aim of this research project is to extend this modular digit slicing concept to more practical higher order digital filters which are recursive and are of many forms (direct, nondirect, canonic, non-canonic).

This thesis illustrates a typical situation in which theoretical considerations and predictions are used to enhance the value of an experimental investigation. The body of the thesis is in two main parts, the first of which considers the two-dimensional modelling of representative pulsed-power systems while the second describes a number of valuable experimental tools that were developed for use in investigating the experimental behaviour of such systems.

No description available.

No description available.

Pulse frequency modulation (PFM) is one of a number of pulse time modulation (PTM) techniques which is suitable for the transmission of video or TV signals through optical fibre. Although several PFM transmission systems have been reported over the past few years, those available commercially usually consist of several components. This thesis describes the design of a novel single chip PFM modulator implemented in 2.4 pm CMOS technology. Various design approaches are considered together with a review of circuit and silicon implementation techniques. The fabricated integrated circuit (IC) matches or exceeds the performance of PFM modulators built with commercially available components. The performance of the design is strongly dependent upon its IC layout. A theoretical analysis of the relationship between the folding grade of a transistor and its parasitic capacitances has been undertaken. Novel equations are developed which enable to trade-off design shape against parasitic capacitance. The lowest drain/source capacitance is always achieved at a folding grade of two regardless of the transistor width to length ratio. The equations developed also show that even folding grades generally achieve a lower parasitic capacitance than odd folding grades. Performance tests on prototype ICs have shown that the measurement equipment introduces significant capacitive loading. A novel approach of calculating this capacitive loading from transient measurement results is described. The designed IC was extensively tested in a practical transmission system comprising modulator and demodulator and results of both quantitative and qualitative measurements are reported. At a carrier frequency of 32 MHz and a modulating input signal amplitude of 1 V, the circuit achieves a harmonic and non-linear distortions of -37.87 dB and -56 dB, respectively. These values compare favourably with published results of PFM systems. Further in system tests confirmed that the IC developed is well suited for the transmission of high quality still and moving pictures. The IC was only compared with the VCO circuits available commercially (Plessey SP1658 and TI SN74S124) since VCOs are the main building block of a PFM modulator and single chip versions are not currently available. Results of the comparison show that the performance of PFM modulators, based on those VCOs, is inferior to the designed circuit whilst requiring a much higher power dissipation. The power dissipation of the designed circuit is 47.5 mW compared to 165 mW and 525 mW for the SP1658 and SN74S124, respectively. Due to the much reduced power dissipation, almost no heat is dissipated from the designed circuit. When operated at its maximum frequency (~ 40 MHz) the temperature of the IC was found to be only 3°C above room temperature.

This Project involved the development of a simulation of a rectangular array of Processing Elements (PE's), with a dedicated frame based knowledge representation language. The main objective of the Project was to analyse and quantify the gain in speed of execution in a parallel environment, as compared with serial processing. The computational model of the language consisted of two main components: the knowledge base, and the replicated/distributed inference engine. The knowledge base was assumed to represent real world knowledge, in that it consisted of a large volume of information, which was divided into domains and hierarchies. When a query is made, appropriate portions of the knowledge base are mapped to the array of PEs on a one-to-one basis (one frame/PE), where each PE is capable of performing any relevant operations itself. The execution of a query is based on the propagation of messages across the array of PEs, where each message is contained in a data packet. Each packet holds the query-frame, created by interacting with the user, together with other relevant information used for knowledge manipulation. The main inference mechanism in the system is based on the parallel inheritance of properties, where each data packet carries inherited data from higher level to lower level frames, within the appropriate hierarchies. As each packet arrives at a PE which contains a relevant frame, a series of matching, and consequently, inheritance operations are performed. An algorithm, superimposed at the highest level of the system, computes time delays in relation to the overall architecture of the machine. There are two main operations for which time penalties are calculated : frame-processing and communication. The frame processing involves matching and inheritance operations, and the communication operation involves message passing and data packet traversal. During each execution cycle, the time penalties for both processing and communication are computed and stored in a file. These files are then used by a graphics package which transforms the numerical data into a set of graphs. These graphs are utilised in the analysis of the behaviour of the simulation. The analysis of the test-runs, and of their associated graphs, has yielded positive and encouraging results, demonstrating that there can be an average of a 35 fold gain in the speed of execution.

The implementation of an automatic fault diagnosis approach for analogue circuits is facing a number of problem areas. They are typically: component and measurement tolerances, circuit size, limited observability constraints, multiple fault conditions, non-linear behaviour, speed and generic applicability. Since such fault finding techniques utilize circuit simulations sometime during the diagnostic process, the preferred form of classification amongst researchers is a taxonomy of Simulationbefore-Test (SbT) and Simulation-after-Test (SaT) methods. A survey of related work following these two strategies has been carried out, which concludes: The main advantage of the SaT strategy is their diagnostic power to cope with above problem areas, their main disadvantage is the often considerable computational on-line effort. The main advantage of the SbT strategy is on-line speed, but diagnostic power is often limited. What is needed is a workable solution to combine the advantages of the two strategies, whilst minimizing their disadvantages. The thesis is focused on this need. Subject of the research programme was therefore to look into the feasibility of a Simulation-before-Test approach for diagnosing toleranced analogue non-linear networks in the presence of multiple faults and from there to research the concepts, strategies and algorithms required to form a diagnostic approach.

No description available.

No description available.