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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

Evaluation of stochastic optimisation algorithms for induction machine winding fault identification

Alamyal, Mohamoud Omran A. January 2013 (has links)
This thesis is concerned with parameters identification and winding fault detection in induction motors using three different stochastic optimisation algorithms, namely genetic algorithm (GA), tabu search (TS) and simulated annealing (SA). Although induction motors are highly reliable, require low maintenance and have relatively high efficiency, they are subject to many electrical and mechanical types of faults. Undetected faults can lead to serious machine failures. Fault identification is, therefore, essential in order to detect and diagnose potential failures in electrical motors. Conventional methods of fault detection usually involve embedding sensors in the machines, but these are very expensive. The condition monitoring technique proposed in this thesis flags the presence of a winding fault and provides information about its nature and location by using an optimisation stochastic algorithm in conjunction with measured time domain voltage, stator current data and rotor speed data. This technique requires a mathematical ABCabc model of the three-phase induction motor. The performance of the three stochastic search methods is evaluated in this thesis for their use to identify open-circuit faults in the stator and rotor windings of a three-phase induction motor. The proposed fault detection technique is validated through the use of experimental data collected under steady-state operating conditions. Time domain terminal voltages and the rotor speed are used as input data for the induction motor model while the outputs are the calculated stator currents. These calculated currents are compared to the measured currents to produce a set of current errors that are integrated and summed to give an overall error function. Fault identification is achieved by adjusting the model parameters off-line using the stochastic search method to minimise this error function. The estimate values for the winding parameters give the best possible match between the performance of the faulty experimental machine and its mathematical ABCabc model. These estimates of the values of the motor winding parameters are used in the detection of the development of faults by identifying both the location and the nature of the winding fault. The effectiveness of the three stochastic methods to identify stator and rotor winding faults are compared in terms of the required computation resources and their success rates in converging to a solution.

Embedded dynamic programming networks for networks-on-chip

Al-Dujaily, Ra'ed January 2013 (has links)
Relentless technology downscaling and recent technological advancements in three dimensional integrated circuit (3D-IC) provide a promising prospect to realize heterogeneous system-on-chip (SoC) and homogeneous chip multiprocessor (CMP) based on the networks-onchip (NoCs) paradigm with augmented scalability, modularity and performance. In many cases in such systems, scheduling and managing communication resources are the major design and implementation challenges instead of the computing resources. Past research efforts were mainly focused on complex design-time or simple heuristic run-time approaches to deal with the on-chip network resource management with only local or partial information about the network. This could yield poor communication resource utilizations and amortize the benefits of the emerging technologies and design methods. Thus, the provision for efficient run-time resource management in large-scale on-chip systems becomes critical. This thesis proposes a design methodology for a novel run-time resource management infrastructure that can be realized efficiently using a distributed architecture, which closely couples with the distributed NoC infrastructure. The proposed infrastructure exploits the global information and status of the network to optimize and manage the on-chip communication resources at run-time. There are four major contributions in this thesis. First, it presents a novel deadlock detection method that utilizes run-time transitive closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in NoCs. This detection scheme, TC-network, guarantees the discovery of all true-deadlocks without false alarms in contrast to state-of-the-art approximation and heuristic approaches. Second, it investigates the advantages of implementing future on-chip systems using three dimensional (3D) integration and presents the design, fabrication and testing results of a TC-network implemented in a fully stacked three-layer 3D architecture using a through-silicon via (TSV) complementary metal-oxide semiconductor (CMOS) technology. Testing results demonstrate the effectiveness of such a TC-network for deadlock detection with minimal computational delay in a large-scale network. Third, it introduces an adaptive strategy to effectively diffuse heat throughout the three dimensional network-on-chip (3D-NoC) geometry. This strategy employs a dynamic programming technique to select and optimize the direction of data manoeuvre in NoC. It leads to a tool, which is based on the accurate HotSpot thermal model and SystemC cycle accurate model, to simulate the thermal system and evaluate the proposed approach. Fourth, it presents a new dynamic programming-based run-time thermal management (DPRTM) system, including reactive and proactive schemes, to effectively diffuse heat throughout NoC-based CMPs by routing packets through the coolest paths, when the temperature does not exceed chip’s thermal limit. When the thermal limit is exceeded, throttling is employed to mitigate heat in the chip and DPRTM changes its course to avoid throttled paths and to minimize the impact of throttling on chip performance. This thesis enables a new avenue to explore a novel run-time resource management infrastructure for NoCs, in which new methodologies and concepts are proposed to enhance the on-chip networks for future large-scale 3D integration.

The accuracy of filtered basis functions for the first principles modelling of defects in semiconductors

Shrif, Fadil Ezzedin Irhoma January 2013 (has links)
This work presents the results of calculations using filtered basis functions performed with the ab initio modelling program (AIMPRO). The filtration method works by projecting out (filtering) components of a reference basis function that are not required for a description of the occupied states, thereby producing functions that are localised in energy. This leads to a significant reduction in the number of functions that are needed. It is demonstrated that when studying diamond, silicon and defects in these materials, the use of filtered basis sets using just four basis functions per atom can achieve a comparable accuracy to conventional calculations that use 30–40 basis functions. This enables a massive increase in computational efficiency that could have far reaching consequences for first principles modelling calculations. The accuracy of the filtration method is first examined for the bulk materials diamond and silicon, in which the energy, lattice constant, bulk modulus and band structure are studied. It is shown that the filtration approximation applied with an efficient spatial cut-off is able to reproduce current calculated values for these to a very high degree of accuracy. A study of the energies of various reconstructed surfaces in diamond and silicon is then presented. It is first demonstrated that the AIMPRO modelling software without filtration reproduces previous published values of surface energies to within about 100 meV per 1x1 surface cell, with this difference being related to different choices for the pseudo-potential and other details of the calculation. It is also demonstrated that iv changes of this degree also occur when changing the exchange-correlation functional used to model the surface. In contrast, the use of filtered basis sets changes these energies by only 1–2 meV, one hundred times smaller, indicating the excellence of this approach and showing that filtered basis calculation with efficient cut-off radii are of essentially equal quality to those of conventional localised basis functions. Finally a series of defect structures in diamond is considered, including both native defects and nitrogen containing defects. Properties studied include formation energies, binding energies, localised vibrational modes, and hyperfine coupling matrices. In all these cases it is shown that the filtration method produces results which closely match those with conventional basis sets and demonstrate that this method has excellent potential for modelling defecting semiconductor structures in the future. The asymptotic speed up of two to three orders of magnitude will then enable a new range of systems with significantly increased size and complexity to be modelled.

Complementary JFET logic in silicon carbide

Habib, Hassan January 2013 (has links)
In the last decade or so, many prototype SiC devices and logic circuits have been demonstrated which have surpassed the performance of Si for the ability to function in extreme environments. The advance of silicon carbide technology has now reached a stage where commercialisation of high performance and energy efficient miniaturised devices and circuits is possible. These devices and circuits should be able to operate on the limited power resources available in harsh and hot hostile environments. These improvements require refining, experimenting and perhaps re-designing devices which can rightly claim their share in the current silicon dominant market. Consequently, there is a need for accurate simulation models for device engineers to understand device and circuit behaviour, examine performance trade-offs and verify the manufacturability of the design. This work includes the first comprehensive study, to the author’s knowledge, on the development and validation of 4H-SiC model parameters for high temperature, low power technology computer aided design (TCAD) finite element (FE) simulations. These model parameters are based on the physical and material properties of 4H-SiC and are derived from published data. The validation of these model parameters is performed using high temperature 4HSiC lateral junction field effect transistor (JFET) data, fabricated and characterised by our group at Newcastle University. TCAD tools and statistical techniques, such as design of experiment (DoE) and response surface modelling (RSM), play a key role in research to model and optimise semiconductor processes. These tools and statistical techniques also aid in studying the impact of process variability on device and circuit performance which ultimately affects the manufacturability and yield of the circuit. Based on TCAD tools and DoE and RSM statistical techniques, a iii systematic methodology is devised to optimise high temperature, four terminal SiC JFETs. Using calibrated FE simulation model, enhancement mode 4H-SiC (normally off) n- and p-JFETs are optimised for operation in extreme environments. The normally-off nature of these devices is desirable for logic devices in terms of reduced gate drive complexity and power dissipation. Unlike previously reported devices, the optimised SiC JFETs are designed such that not only the gate length is reduced to 2 μm (in contrast to the 10 μm reported elsewhere), but are also able to operate over a temperature range of −50 °C to 600 °C on a fixed voltage of 2 V, in contrast to the 20 V used in other work. Furthermore, the drain saturation current of the optimised JFETs increase with temperature which allows high on-to-off state current-ratio (Ion/Ioff) at elevated temperatures. High Ion/Ioff is essential for low power logic circuitry with fast switching. At 500 °C, Ion/Ioff ~ 103 for optimised (simulated) JFET as opposed to < 102 reported elsewhere. This is achieved by the choice of optimal gate bias, |Vg| = 2 V. The fourth, back-gate, terminal in the optimised JFET design provides an alternative route to tackle process variability. The effect of varying back-gate bias (Vsub) on the device performance parameters, such as threshold voltage (Vt), drain saturation current (Idss) and channel leakage current (Ioff) is also studied in detail. Using enhancement mode n- and p-JFETs, logic circuitry based on 4H-SiC complementary JFET (CJFET) technology is described for the first time, to the author’s knowledge. In order to assess the potential improvements in performance of digital logic functions as a result of using CJFET technology in their implementation, the static and dynamic characteristics of the most basic logic element, namely the inverter, are analysed using calibrated FE simulation model. The design and analysis of an inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. The static and dynamic characteristics of CJFET logic inverters are analysed against operating frequency, temperature, supply voltage and fan-out. At 500 °C and operating at a supply voltage of 2 V, the inverter has noise margin high = 0.36 V, noise margin low = 0.57 V, undefined iv region = 0.51 V, propagation delay = 7ns, slew rate = 29.5 V/μs, maximum switching frequency = 10.6 MHz and static power = 353 nW. Apart from speed, these static and dynamic characteristics of the CJFET logic inverter, at 500 °C, are found to be comparable to those of silicon and strained silicon technology, at room temperature (RT). Currently, one of the biggest challenges faced by SiC technology in the development of complex ICs is high static power dissipation at 500 °C (~ 10−3 W). With the supply voltage scaled to 1 V, the static power of a CJFET inverter can further be reduced to 20.6 nW, but at an expense of degrading noise margin high to 0.15 V and noise margin low to 0.36 V. Finally, in CJFET logic arrays, random variations in manufacturing process parameters can cause significant variations in neighbouring gates or transistors and, therefore, can largely be accountable for poor yield. Using DoE and RSM based statistical approach, the effect of (±10%) process variability on CJFET logic inverter’s stability, in terms of noise margins, and efficiency, in terms of static power dissipation, are modelled and analysed at RT and 500 °C. It is found that the gate implant depth (tg) and channel doping (ND) have the most significant effect on the studied inverter responses. The fluctuation in these process parameters causes variations in threshold voltage (Vt) of the device which in turn affects the performance of the logic gate. However, these Vt variations can be tackled by the use of epitaxial gated devices which eliminate the issue of tg variations and by the adjustment of back-gate biasing (Vsub). Furthermore, with the continuing advances in SiC wafer quality, with minimum tolerances, it is inevitable that soon SiC CJFET technology can be integrated with SiC gas sensors for monitoring extreme environments.

MOSFET strain sensor for microcantilevers

Wang, Yao January 2014 (has links)
Microcantilever structure was used to design and fabricate strain sensors. P-channel MOSFETs were designed and fabricated for strain sensors as hole mobility under uniaxial stress has higher mobility enhancement than that of electron mobility under either uniaxial stress or biaxial stress. For MOSFET sensors on microcantilevers, anchor area is the traditional position for sensors due to its highest stress. The aim of this research is to investigate the assumption of biaxial stress at the anchor area which makes the anchor location less sensitive. COMSOL software was employed to simulate stress profiles in silicon beams. Four-pointbending provides almost uniaxial stress at the surface, but cantilever bending generates biaxial stress at the anchor region but uniaxial stress away from anchor. The transverse stress at the anchor region increases with the bending and is depends on the longitudinal stress. In this research, the sensitivity of the sensor at the cantilever anchor was lower than that under uniaxial stress from four-point-bending measurement. It is suggested that the transverse stress at the anchor region will degrade the sensitivity compared to that under uniaxial stress. Although narrower cantilever provides higher longitudinal stress at the anchor, it brings higher transverse stress at the anchor as well. Possible solutions such as employing stressed layer, holes and slots were proposed to reduce the transverse stress without impact on the longitudinal stress, thus to increase the sensitivity. In comparison, employing slots is recommended as the transverse stress can be concentrated to nearly zero at the slot region with enhanced and elongated longitudinal stress.

Computer models for representing electrical machines during switching transients

Guardado, J. L. January 1989 (has links)
Switching transients produce steep fronted waves (prestrikes or restrikes) which reach the machine terminals producing severe dielectric stresses in the winding insulation. The object of this study is to develop computer models for calculating the surge distribution in the winding during switching transients as well as to obtain a machine terminal representation. Beginning with a very simple model valid for very short periods of time, the computer models are extended and finally a full machine winding model is presented. The computer models developed cover a broad time and frequency range and they are based on multiconductor transmission line theory. Several phenomena like the flux penetration into the iron and the stator inter-coil coupling are studied and incorporated into the solutions. The thesis also describes several application studies using the computer models developed. The studies include a sensitivity analysis from which guidelines for reducing the dielectric stresses in the winding insulation are suggested. Using convolution techniques and measurements on machine terminals, a technique for a better assessment of the dielectric stresses in the coils during real switching transients is presented. Finally, the computer results are supported by a comprehensive set of measurements carried out on a 6.6 KV. 1690 KW. machine winding

The characteristics and feasibility of an in-line debris control technique for KrF excimer laser ablative micromachining

Dowding, Colin F. January 2009 (has links)
To observe KrF excimer laser ablation through thin liquid film of de-ionized (DI) water and the effects thereof on debris control, equipment was designed to contain a small control volume that could be supplied with a fixed flow velocity thin film of DI water to immerse a bisphenol A polycarbonate workpiece. Using the same equipment comparison with ablation in ambient air was possible. The positional debris deposition of samples machined in ambient air was found to show modal tendency reliant on the feature shape machined and according to species size. This is proposed to be due to the interaction of multiple shockwaves at the extent of ablation plumes generated at geometry specific locations in the feature. Debris was deposited where the shockwaves collide. Ablating under a flowing thin film of DI water showed potential to modify the end position and typical size of the debris produced, as well as increased homogeneity of deposition density. Compared with a sample machined in ambient air, the use of immersion has reduced the range of debris deposition by 17% and the deposition within the boundary of the ablation plume has a comparatively even population density. Unlike samples machined in ambient air, outside the ablation plume extents positional control of deposited debris by thin film flowing DI water immersion was evidenced by rippled flow line patterns, indicating the action of transport by fluid flow. A typical increase in debris size by an order of magnitude when using DI water as an immersing liquid was measured, a result that is in line with a colloidal interaction response.

Control of charge transports in semiconductor superlattices using an acoustic wave

Awodele, M. Kofoworola January 2014 (has links)
In this work, we describe the electron dynamics in semiconductor superlattices (SLs) when driven by an acoustic wave. First, we discuss the physical features and structure of SLs. Then we describe semiclassical transport in periodic potential driven by a plane wave, and the dynamics of ultracold atoms in the periodic potentials. Secondly, we explore single electron dynamics in superlattices driven by an acoustic wave, then present and analyse the types of electron trajectories according to the strength of the acoustic wave amplitude. The two dynamical regimes obtained depend on the wave amplitude strength and the initial position of electrons in the acoustic wave. The frequency range of the oscillation produced can be as large as terahertz. Lastly, we discuss the effect of applying a static electric field to the acoustically driven SLs. When the acoustic wave and electric fields were applied together along the axis of SLs, we obtained a higher peak drift velocity than when the acoustic wave or electric fields were applied alone. We use the phase portrait to explain the electron trajectory and the path of the electrons. The global state associated with the drastic change in the drift velocity of the electrons depends on the varied parameters in the dynamical systems. We numerically calculate the electron trajectories while we varied the strength of electric field and wave amplitude to investigate the role of interactions in the system. When very high electric field and very high wave amplitude are applied together along the axis of SL, global catastrophe occurs. This is the discontinuous bifurcation in dynamical system.

Feed-forward linearisation of a directly modulated semiconductor laser and broadband millimetre-wave wireless over fibre systems

Ismail, T. January 2007 (has links)
This thesis is concerned with reduction of non-linear distortion in a directly modulated uncooled semiconductor laser using feed-forward compensation and investigating the performance of broadband millimetre-wave wireless over fibre systems. One of the key elements that determine the performance in a fibre optic link is the linearity of the optical source. Direct modulation of an uncooled semiconductor laser diode is a simple and cost effective solution. However, the distortion and noise generated by the laser limit the achievable dynamic range and performance in a system. Feed-forward linearisation is demonstrated at 5 GHz, the highest operating frequency reported, with 26 dB third order intermodulation distortion suppression and simultaneous noise reduction leading to enhanced spurious free dynamic range of 107 dB (1Hz). The effectiveness of feed-forward in a multi-channel system is investigated. Laser non-linearity can cause spectral re-growth and interchannel distortion that can completely mask the adjacent channel. A significant 11 dB interchannel distortion suppression and 10.5 dB power advantage is obtained compared to the non-linearised case. These results suggest that feed-forward linearisation arrangement can make a practical multi-channel or multi-operator wireless over fibre system. In the second part of this thesis the first experimental transmission of wireless data over fibre with remote millimetre-wave local oscillator delivery using a bi-directional semiconductor optical amplifier in a full duplex system with 2.2 km coarse wavelength division multiplexing fibre ring architecture is demonstrated. The use of bi-directional SOAs in place of unidirectional erbium doped fibre amplifier or unidirectional SOAs, together with the use of CWDM and optical distribution of the local oscillator signal allow substantial reduction in overall complexity and cost. Successful transmission of data over 12.8 km fibre is achieved with clear and well defined constellations and eye diagrams as well as 10.5% and 7.8 % error vector magnitude values for the downlink and uplink directions, respectively. The thesis also presents an implementation and performance of a millimetre-wave gigabit wireless over fibre system. CWDM devices such as uncooled laser diodes and passive components are used for the first time in a gigabit system allowing cost savings compared to dense WDM. This makes such solutions more attractive for millimetre-wave access systems. Optically modulated gigabit wireless data signals to and from the base stations are distributed at 5 GHz and up-converted using a remotely delivered LO source. Eye diagrams and bit error rate are measured to assess the system performance.

Local characterisation of strain in silicon nanostructures

Ureña Begara, Fernando January 2014 (has links)
Strain engineering is used in the microelectronics industry for fabricating micro- and nano-electromechanical systems (MEMS and NEMS) and state-of-the-art metal-oxide-semiconductor field-effect transistors (MOSFETs). In these devices suspended silicon beams, films and nanowires are widely used. However, the mechanical, thermal and electrical properties of silicon change significantly at the nanoscale. Therefore, an accurate knowledge of the size effect on these properties, the role of the surface and an accurate characterisation of the stress and strain distribution in these devices is needed for a complete understanding of the device operation. Likewise, state-of-the-art MOSFETs incorporate strain into the channel to improve performance due to a carrier mobility enhancement compared with unstrained silicon channel transistors. However, the mobility enhancement especially at high vertical electric fields (where commercial MOSFETs operate), is still not well understood. The SiO2/Si interface roughness exhibits, at the nanoscale, scaling behaviour with the scale of observation. However, to date, there is no experimental study of the SiO2/Si interface roughness scaling behaviour with strain. This study is needed to better understand the surface roughness scattering-limited mobility of electrons and holes in strained devices. Raman spectroscopy is a widely used technique to characterise strain. However, the conversion of Raman peak shifts to strain values requires a strain-shift coefficient. Traditionally, the reported strain-shift coefficients have been determined from experiments performed in bulk material. The applied stress has also been limited within the range 0 – 2 GPa. This range is reasonable for bulk silicon characterisation but is too narrow for silicon nanostructures and devices where higher stress values are often favourable for improving performance. Consequently, there is an outstanding need to find appropriate strain-shift coefficients for silicon nanowires and thin films under large values of stress. In this thesis strain in silicon nanostructures is experimentally and theoretically investigated for strain values ranging from 0 to 3.6%. Strain has been characterised using scanning electron microscopy (SEM), Raman spectroscopy, and theoretically with analytical calculations and finite element simulations. The combination of these techniques and the large number of samples (up to 85) has allowed the accurate determination of the ii strain-shift coefficient for the technologically important (100) silicon surface and for stress values up to 4.5 GPa. The work also enables a better understanding of the changes in silicon properties with strain when device dimensions are reduced to the nanoscale. The size dependency of the Young‟s modulus, fracture strain, thermal conductivity and the role of the surface in the size dependent physics are also investigated. It is found that some properties such as the fracture strain change with the dimensions of the sample whereas others such as the Young‟s modulus and thermal conductivity do not change. Finally, the impact of uniaxial and biaxial strain on the surface roughness of silicon nanostructures and thin films has been analysed by atomic force microscopy (AFM). It is found that the silicon surface roughness changes in different manner with uniaxial and biaxial strain. The results show that the silicon surface roughness is self-affine with strain and that this behaviour has to be considered within the models used to describe the carrier mobility in MOSFETs at high vertical electric fields.

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