The aggressive scaling of CMOS process technology has been driving the rapid growth of the semiconductor industry for more than three decades. In recent years, the performance gains enabled by CMOS scaling have been increasingly challenged by highlyparasitic on-chip interconnects as wire parasitics do not scale at the same pace. Emerging 3D integration technologies based on vertical through-silicon vias (TSVs) promise a solution to the interconnect performance bottleneck, along with reduced fabrication cost and heterogeneous integration. As TSVs are a relatively recent interconnect technology, innovative test structures are required to evaluate and optimise the process, as well as extract parameters for the generation of design rules and models. From the circuit designer’s perspective, critical TSV characteristics are its parasitic capacitance, and thermomechanical stress distribution. This work proposes new test structures for extracting these characteristics. The structures were fabricated on a 65nm 3D process and used for the evaluation of that technology. Furthermore, as TSVs are implemented in large, densely interconnected 3D-system-on-chips (SoCs), the TSV parasitic capacitance may become an important source of energy dissipation. Typical low-power techniques based on voltage scaling can be used, though this represents a technical challenge in modern technology nodes. In this work, a novel TSV interconnection scheme is proposed based on reversible computing, which shows frequencydependent energy dissipation. The scheme is analysed using theoretical modelling, while a demonstrator IC was designed based on the developed theory and fabricated on a 130nm 3D process.

The extreme properties of diamond combined with the emergence of chemical vapour deposition (CVD) techniques for the growth of large area free standing diamond wafers has led to considerable interest in the use of this material for electronic applications. However, to date, the polycrystalline nature of the material grown by heteroepitaxy has hindered progress in this field leading to only niche applications for diamond electronics being identified. Whilst homoepitaxial growth seemed to be a solution to counter this issue, the substrate cost and the lack of a suitable dopant for -type conductivity together with the relatively large activation energy of p-type dopants reduced the effectiveness of electronic devices made from diamond. Finally, the low growth rates using standard microwave CVD techniques remains a problem. This thesis presents electronic characterisation of such homoepitaxial films using Hall effect measurements. The observation of p-type character of the surface conductivity due to hydrogen termination was confirmed and a correlation between the transport properties and the film thickness was demonstrated. In addition to Hall effect measurements, SEM/STM data are presented and the parameters for high growth rates of these overlayers are revealed. Passivation of these layers has also been investigated so that the p-type character and hence the device operation is not lost at higher temperatures when the devices are operated in air. A newly developed material, ultrananocrystalline diamond (UNCD), has been studied for its -type character. Hall effect measurements revealed the conductivity of this material is strongly influenced by the addition of nitrogen into the source gases and UNCD becomes conductive with low thermal activation energy. Finally, impedance spectroscopy measurements were taken on both UNCD and phosphorus doped material to investigate the conduction paths in both materials that lead to the -type conductivity observed in both kind of materials. The likely impact of the realisation of more effective processes for both growth and doping, described here, for the development of electronic devices from diamond is discussed.

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