The Viterbi Algorithm is a popular method for decoding convolutional codes, receiving signals in the presence of intersymbol-interference, and channel equalization. In 1981 the European Telecommunications Administration (CEPT) created the Groupe Special Mobile (GSM) Committee to devise a unified pan-European digital mobile telephone standard. The proposed GSM receiver structure brings together Viterbi decoding and equilization. This thesis presents three VLSI designs of the Viterbi Algorithm with specific attention paid to the use of such modules within a GSM receiver. The first design uses a technique known as redundant number systems to produce a high speed decoder. The second design uses complementary pass-transistor logic to produce a low-power channel equalizer. The third design is a low area serial equalizer. In describing the three designs, redundant number systems and complementary pass-transistor logic are examined. It is shown that while redundant number systems can offer significant speed advantages over twos complement binary, there are other representations that can perform equally well, if not better. It will also be shown that complementary pass-transistor logic can offer a small improvement for VLSI circuits in terms of power consumption.

Improvements in semiconductor technology have supported an exponential growth in microprocessor performance for many years. The ability to continue on this trend throughout the current decade poses serious challenges as feature sizes enter the deep sub-micron range. The problems due to increasing power consumption, clock distribution and the growing complexity of both design and verification, may soon limit the extent to which the underlying technological advances may be exploited. One approach which may ease these problems is the adoption of an asynchronous design style - one in which the global clock signal is omitted. Commonly-cited advantages include: the ability to exploit local variations in processing speed, the absence of a clock signal and its distribution network, and the ease of reuse and composability provided through the use of delay-insensitive module interfaces. While the techniques to design such circuits have matured over the past decade, studies of the impact of asynchrony of processor architecture have been less common. One challenge in particular is to develop multiple-issue architectures that are able to fully exploit asynchronous operation. Multiple-issue architectures have traditionally exploited the determinism and predictability ensured by synchronous operation. Unfortunately, this limits the effectiveness of the architecture when the clock is removed. The work presented in this dissertation describes in detail the problems of exploiting asynchrony in the design of superscalar processors. A number of techniques are presented for implementing both data forwarding and dynamic scheduling mechanisms, techniques that are central to exploiting instruction-level parallelism and achieving high-performance. A technique called instruction compounding is introduced, which appends dependency information to instructions during compilation, which can be exploited at run-time. This simplifies the implementation of both the dynamic scheduling and data-forwarding mechanisms.

In many practical applications, one sensor is only available to record a mixture of a number of signals. Single-channel blind signal separation (SCBSS) is the research topic that addresses the problem of recovering the original signals from the observed mixture without (or as little as possible) any prior knowledge of the signals. Given a single mixture, a new pseudo-stereo mixing model is developed. A “pseudo-stereo” mixture is formulated by weighting and time-shifting the original single-channel mixture. This creates an artificial resemblance of a stereo signal given by one location which results in the same time-delay but different attenuation of the source signals. The pseudo-stereo mixing model relaxes the underdetermined ill-conditions associated with monaural source separation and begets the advantage of the relationship of the signals between the readily observed mixture and the pseudo-stereo mixture. This research proposes three novel algorithms based on the pseudo-stereo mixing model and the binary time-frequency (TF) mask. Firstly, the proposed SCBSS algorithm estimates signals’ weighted coefficients from a ratio of the pseudo-stereo mixing model and then constructs a binary maximum likelihood TF masking for separating the observed mixture. Secondly, a mixture in noisy background environment is considered. Thus, a mixture enhancement algorithm has been developed and the proposed SCBSS algorithm is reformulated using an adaptive coefficients estimator. The adaptive coefficients estimator computes the signal characteristics for each time frame. This property is desirable for both speech and audio signals as they are aptly characterized as non-stationary AR processes. Finally, a multiple-time delay (MTD) pseudo-stereo SINGLE CHANNEL SIGNAL SEPARATION ii mixture is developed. The MTD mixture enhances the flexibility as well as the separability over the originally proposed pseudo-stereo mixing model. The separation algorithm of the MTD mixture has also been derived. Additionally, comparison analysis between the MTD mixture and the pseudo-stereo mixture has also been identified. All algorithms have been demonstrated by synthesized and real-audio signals. The performance of source separation has been assessed by measuring the distortion between original source and the estimated one according to the signal-to-distortion (SDR) ratio. Results show that all proposed SCBSS algorithms yield a significantly better separation performance with an average SDR improvement that ranges from 2.4dB to 5dB per source and they are computationally faster over the benchmarked algorithms.

The state space of every continuous multi-stable system is bound to contain one or more metastable regions where the net attraction to the stable states can be infinitely-small. Flip-flops are among these systems and can take an unbounded amount of time to decide which logic state to settle to once they become metastable. This problematic behavior is often prevented by placing the setup and hold time conditions on the flip-flop’s input. However, in applications such as clock domain crossing where these constraints cannot be placed flip-flops can become metastable and induce catastrophic failures. These events are fundamentally impossible to prevent but their probability can be significantly reduced by employing synchronizer circuits. The latter grant flip-flops longer decision time at the expense of introducing latency in processing the synchronized input. This thesis presents a collection of research work involving the phenomenon of flip-flop metastability in digital systems. The main contributions include three novel solutions for the problem of synchronization. Two of these solutions are speculative methods that rely on duplicate state machines to pre-compute data-dependent states ahead of the completion of synchronization. Speculation is a core theme of this thesis and is investigated in terms of its functional correctness, cost efficacy and fitness for being automated by electronic design automation tools. It is shown that speculation can outperform conventional synchronization solutions in practical terms and is a viable option for future technologies. The third solution attempts to address the problem of synchronization in the more-specific context of variable supply voltages. Finally, the thesis also identifies a novel application of metastability as a means of quantifying intra-chip physical parameters. A digital sensor is proposed based on the sensitivity of metastable flip-flops to changes in their environmental parameters and is shown to have better precision while being more compact than conventional digital sensors.

In modern wormhole-routed multicomputer interconnection networks, contention plays an increasingly significant role in limiting performance at high loads, especially if there is poor communication locality in the workload or if the communication load is non-uniform. However, the relationship between the level of contention in the communication network and performance degradation in a running workload is complex. At high loads, the communication network may be affecting the rate of injection of new packets into the network just as much as the workload's packet injection rate is affecting performance in the network. In this thesis we will aim to provide a way of untangling this relationship. We will present a methodology based on discrete event simulation which will allow us to separately identify the cost of contention to a running program, and the amount of contention actually occurring. We describe a dedicated discrete event simulator used to host performance evaluations of a set of workloads on a 2-D mesh of wormhole routing elements based on the T9000 transputer and its associated C104 routing device. Our simulator is capable of selectively running without contention effects, allowing us to observe not only the amount of contention taking place in the network but also the performance degradation it is causing relative to an ideal, contention-free environment. We describe a set of metrics which can be used to measure these contention effects. We make a strong distinction between contention internal to the communication network and contention taking place at or before the injection buffers into the network: these are shown to have very different implications for performance. We also describe a method of classifying synchronisation properties of workloads for which packet injections are not necessarily independent. If there is a feedback loop between network performance and workload performance, then we need to understand if and how the workload may react to changes in the network's performance before we can predict the impact of contention. Finally we show that the workload classifications and contention metrics we have identified do allow us to distinguish between different levels of workload sensitivity to contention in our networks.

The proposed approach to estimate multiple frequency trajectories and amplitude envelopes of multiple non-stationary sinusoids is then presented in chapter 4. There, the ideas are focused on the design of an algorithm to adapt the zeros of a filter, structured in cascade form, to track multiple non-stationary frequencies. Although this approach has been used in the past to analyse non-stationary multicomponent exponentials signals, the novel technique introduces a new gradient-based algorithm focused on the direct estimation and tracking of the instantaneous frequency of each component of the signal. A second algorithm is also proposed in chapter 4 to estimate the amplitude envelope of a non-stationary sinusoid relying on two consecutive samples. This algorithm is extended to the multicomponent case by first isolating each sinusoid, relying on a cascade of notch filters. The theoretical propositions are validated in computer simulations of the algorithm for the case of synthetic signals, a bat sonar signal and a voiced segment of speech. In chapter five, a spatial filter in decomposed form is used to analyse computer simulations of signals from a linear array of uniformly spaced sensors over which impinge multiple non-stationary plane waves. The ideas exploited constitute an extension to the spatial domain of direct frequency estimation using gradient-descent techniques. The resulting decoupled adaptive filter allows the tracking of the instantaneous spatial frequency of each component of the directional signal, which is equivalent to tracking the angle at which the different plane waves impinge on the array.

Multimedia communication will be an important application in future wireless communication. The second-generation mobile communication systems already support basic multimedia services such as voice, text-messaging services and still-imaging communication. However, next generation wireless communication technology combined with advances in integrated circuit design and process fabrication technology will allow more data to be processed and transmitted through wireless channels. This will lift the current barriers and enable more demanding multimedia applications such as video telephony, video conferencing and video streaming. Video compression plays an important role in today's wireless communications. It allows raw video data to be compressed before it is sent through a wireless channel. However, video compression is compute-intensive and dissipates a significant amount of power. This is a major limitation in today's portable devices. Existing multimedia devices can only play video applications for a short time before the battery is depleted. This limits the user's entertainment experience and becomes a major bottleneck for the development of more attractive applications. The focus of this thesis is to design a low power video compression system for wireless communication. in this thesis, we propose techniques to minimise the power consumption at the algorithmic and architectural level. The low power is achieved by minimising the switching power between interacting modules that contribute to major the power consumption in H.264 standard. Motion estimation (ME) has been identified as the main bottleneck in MPEG video compression, including in the H.264 system where it takes up to 90% of the coding time. To reduce the power consumption in motion estimation hardware architecture, we have proposed a two-step algorithm that minimises the memory bandwidth and computational load of the ME. In this technique, the search is performed in low resolution mode at the first stage followed by high resolution mode in the second stage. This method reduces the total computation and memory access compared to the conventional method without significantly degrading the picture quality. The simulation results show that the proposed method gives good PSNR as compared to the conventional full search with PSNR drop < 0.5dB. An energy efficient hardware for implementing the proposed two-step method is suggested. The architecture is able to perform both low resolution and high resolution searches without significantly increasing the area overhead. With a unique pixel arrangement, the proposed method is able to perform at both low resolution and high resolution while still being able In to reduce the memory bandwidth. The results show that the proposed architecture is able to save up to 53% energy as compared to the conventional full search architecture.

Wireless communications is rapidly moving towards so called 4G wireless systems. This has led to an increasing demand to develop integrated mobile terminals which have multi-mode capabilities, i.e. multiple communication systems can coexist. The central goal of this thesis is to determine appropriate structures and algorithms for multi-mode receivers that maximize flexibility without excessive compromise in performance. The work develops multi-mode terminals from the algorithm viewpoint, reducing receiver complexity by taking advantage of the commonalities among different specifications and receiver requirements. For example, the commonalities among DAB, DVB-T and HIPERLAN-2 physical layers are investigated and a common system clock is adopted for these communication systems. In addition, a receiver architecture combining sampling rate conversion and OFDM symbol synchronisation is also presented. The coexistence of WCDMA and OFDM systems from the perspective of using the same equalisation structure is elaborated; chip-level frequency domain equalisation for WCDMA forms a major part of this thesis. Simulation results verify the effectiveness of the proposed equalisation algorithms. Moreover, SC-FDE with more flexible structures, i.e. with a varying length feedback filter or without cyclic prefix, is examined. Then the importance of an accurate channel estimation for practical spread spectrum systems is emphasized. A code-multiplexed pilot sequence is used for the purpose of channel estimation in both WCDMA and CP-CDMA systems and to maintain bandwidth efficiency. System performance is improved significantly by a proposed joint iterative channel estimation and parallel interference cancellation algorithm. Finally conclusions are drawn and suggestions for further work presented.

This thesis is concerned with the estimation of edges in magnetic resonance images (MRI), which may be seen as a first step in the automatic classification of such data. The estimation is taken as a two-stage process. A set of points lying on a single edge is first identified. Secondly, some form of closed curve is fitted to this set of points to describe the edge. The data analysed in this study are MRI of cross-sections through human thighs. Although the subject of the images exists in continuous two-dimensional space, in practice data values are only recorded at discrete, sampled points. This is due to quantisation of the underlying continuous function for storage on a computer. A major theme for this study is the recovery of the underlying continuous function from the sampled data: it is expected that this will allow edges to be estimated more accurately. Bivariate kernel regression is used in the first stage to fit a smooth function to the observed data. Edge points are identified as positions of zero-crossings of the smooth function. The accuracy with which edge points are located is influenced by the amount of smoothing, and several data-based methods are discussed for estimating an appropriate smoothing parameter. In the second stage, an edge is modelled as a simple, closed curve by fitting a Fourier series (FS) to the set of edge points. Geometric properties, such as perimeter length, can be determined from the fitted series. The accuracy of the estimation of such properties is used as a criterion to determine the number of terms to be included in the series. The choice of variable with which to label consecutive points prior to fitting the FS is also discussed.

This thesis investigates the effect of non-stationarity reduction, in the form of silence removal, on the performance of blind separation and deconvolution techniques for speech signals. An information-maximisation-based system is used for the separation of instantaneously mixed signals, and a decorrelating system for convolutively mixed signals. An introduction to the concepts of adaptive signal processing, blind signal processing and artificial neural networks is presented. A review of approaches to solving the blind signal separation and deconvolution problems is provided. The susceptibility of the information-maximisation approach to signal non-stationarity is discussed and two methods of silence identification and removal are compared and used to pre-process data before blind separation. The "infomax" approach is used to separate instantaneous mixtures, and is also modified to incorporate silence assessment and removal techniques to form an on-line system. Further modifications are made to the algorithm to investigate the effect of alternative update strategies, and these are compared with experimental results from identical modifications to diverse separating algorithms. A performance metric is used to assess the quality of separation achieved. The application of these techniques to convolutively mixed speech signals is also investigated, using the CoB1iSS algorithm. The effectiveness of the application of the silence removal techniques to both the time domain and frequency domain representations of the outputs is tested. While this form of non-stationarity reduction improves the rate of convergence for instantaneous mixtures, it does not cause any significant improvement in separation performance under most of the experimental conditions tested. No significant difference in performance was noted for the separation of convolutive mixtures in either the time or frequency domain.