The impact and influence of the Internet as a communications medium cannot be overstated. It has had a profound effect on economic, political, and other social infrastructures, and has introduced ways of communicating which have transformed social relationships. The Internet has opened up information exchange on a global scale, offering enormous opportunities and advantages to an hitherto unknown degree. The Internet has also raised a number of serious, and urgent, ethical challenges. The discussions and debate surrounding ethical issues such as trust, security and privacy, amongst others, conducted at all levels (international, government, academia and the popular press) in themselves are evidence of the complexity of the problem of Internet ethics. The research unravels some of the complexity and muddle of Internet ethics, with the objective of providing a foundation for further research. This thesis offers four perspectives on the problems of Internet ethics: technical, conceptual, regulatory and ethical. These different viewpoints are not only useful in drawing out insights concerning the ethical framework of the Internet, they also provide leverage for the analysis of pertinent issues. The work in this thesis thus offers a framework for understanding, and analysis, which can be developed and used in continuing investigations. The research is a combination of theory and practice - both informing each other. The approach taken arose from the author's direct involvement in many of the expert discussions and debates which (together with the literature), identified a need for foundational work. In-depth work with a number of specialised groups has provided the practical backdrop, and grounding to this research - published results appear as Appendices.

This thesis is concerned with the hardware implementation in VHDL (VHSIC Hardware Description Language) of a Generalised Minimum Distance (GMD) decoder for Reed Solomon (RS) codes. The generic GMD decoder has been implemented for the Reed Solomon codes over GF(28 ). It works for a number of RS codes: RS(255, 239), RS(255, 241), RS(255, 243), RS(255, 245), RS(255, 247), RS(255, 249), and RS(255, 251). As a comparison, a Hard Decision Decoder (HDD) using the Welch-Berlekamp algorithm for the same RS codes is also implemented. The designs were first implemented in MAT LAB. Then, the designs were written in VHDL and the target device was the AItera Field Programmable Gate Array (FPGA) Stratix EP 1 S25-B672C6. The GMD decoder achieved an internal clock speed of 66.29 MHz with RS(255, 251) down to 57.24 MHz with RS(255, 239). In the case of HDD, internal clock speeds were 112.01 MHz with RS(255, 251) down to 86.23 MHz with RS(255, 239). It is concluded that the GMD needs a lot of extra hardware compared to the HDD. The decoder GMD needs as little as 35% extra hardware in the case of RS(255, 251) decoder, but it needs 100% extra hardware for the RS(255, 241) decoder. If there is an option to choose the type of RS code to use, it is preferable to use the HDD decoder rather than the GMD decoder. In real world, the type of RS code to use is usually fixed by the standard regulation. Hence, one of the alternative way to enhance the decoding performance is by using the GMD decoder

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