This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

This thesis proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the front-end filters an oversampling complex discrete-time ΔΣ ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time ΔΣ ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time ΔΣ modulator implementations. This feature makes the proposed discrete- time ΔΣ ADC ideal for multistandard receiver applications.

Test strategies were developed to reduce the overall production testing cost of high-performance data converters. A static linearity testing methodology, aimed at reducing the test time of A/D converters, was developed. The architectural information of A/D converters was used, and specific codes were measured. To test a high-performance A/D converters using low-performance and low-cost test equipment a dynamic testing methodology was developed. This involved post processing of measurement data. The effect of ground bounce on accuracy of specification measurement was analyzed, and a test strategy to estimate the A/D converter specifications more accurately in presence of ground bounce noise was developed. The proposed test strategies were simulated using behavioral modeling techniques and were implemented on commercially available A/D converter devices. The hardware experiments validated the proposed test strategies. The test cost analysis was done. It suggest that a significant reduction in cost can be obtained by using the proposed test methodologies for data converter production testing.

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content.

Στην παρούσα διπλωματική εργασία παρουσιάζεται ο σχεδιασμός και η υλοποίηση ενός καινοτόμου μετατροπέα σήματος (D/A converter ή DAC) με τη δυνατότητα εξωτερικής ρύθμισης (offline calibration) για μετατροπή υψηλής ακρίβειας, η οποία εξασφαλίζει υψηλή γραμμικότητα ανεξαρτήτως της ανοχής των στοιχείων που τον απαρτίζουν. Μόλις ο μετατροπέας ρυθμιστεί κατάλληλα, λειτουργεί αντίστοιχα με ένα DAC, όπου όλα τα στοιχεία του έχουν υποστεί επεξεργασία με λέιζερ (laser trimmed DAC), αλλά χωρίς το υψηλό κόστος κατασκευής που συνεπάγεται η παραπάνω διαδικασία, με αποτέλεσμα να αποτελεί μία ιδανική οικονομική λύση για εφαρμογές που απαιτούν υψηλή ακρίβεια μετατροπής. / This diploma thesis presents the design and implementation of an innovative Digital to Analog Converter (DAC) with the capability of offline external calibration for accurate measurements, which guarantees high linearity regardless of the mismatch of its components. Once the converter has been configured, it can attain the same linearity performance as a laser trimmed DAC, but without the high manufacturing costs involved in the laser etching process, making it an ideal low-cost solution for high accuracy applications.

This thesis deals with the design of a device that enables to monitor the behavior of the measured signal on the computer screen, using the principle of the digital oscilloscope. The control element of the device is the field programmable gate array (FPGA) on FITkit platform.  The FPGA configuration controls the input signal sampling and sends the received samples through the USB interface to the PC. The graphical application implemented in the computer tries to restore the signal and then displays it on the screen.

Diplomová práce obsahuje stručný teoretický základ pro designéra/ku A/D převodníku v technologii CMOS a přehled architektur A/D převodníků používaných v automobilovém průmyslu. Volba vhodné architektury pro konkrétní aplikaci byla zásadním úkolem zpra- covaným v semestrálním projektu předcházejícím tuto práci a je rovněž součástí této práce. Analýza v Matlabu, ze které by mělo vyplynout, je-li třeba zahrnout do architek- tury podblok Sample and Hold, je také součástí práce. Klíčovou částí práce je dokumen- tace návrhu jednotlivých podbloků A/D převodníku – operačního zesilovače, kompará- toru a R-2R D/A převodníku – a ověření jejich funkčnosti. V závěru práce je ověřena funkčnost A/D převodníku jako celku.