Increasing power consumption and heat dissipation are becoming urgent challenges for processors today and in the future. Digital power control architectures in which processors closely interact with voltage regulators are becoming necessary to enhance system energy efficiency. Digital techniques offer advantages such as flexibility, fewer external components and reduced overall cost as compared to conventional analog techniques. The primary objective of this thesis is to develop new digital control architecture for processor voltage regulators with low complexity and high dynamic performance. A digital control technique to naturally implement the desired output impedance is proposed. In this technique, Adaptive Voltage Positioning (AVP) is implemented by generating a dynamic voltage reference and a dynamic current reference to achieve the desired output impedance. A dual-voltage-loop control with dynamic reference step adjustment, non-linear control and a dedicated transient detection circuit is proposed to improve the dynamic performance. The dynamic reference step adjustment method lowers the high speed requirement of reference update clock; the non-linear control minimizes the transient-assertion-to-action delay and maximizes the inductor current slew rate; and the transient detection circuit recognizes the load transient state in a manner adaptive to the amount and slew rate of load transient. Theoretical, simulation and experimental results prove the effective operation and excellent performance of the controller. Finally, the dynamic performance of the voltage regulator with the proposed digital controller under large-step load oscillations is proven by simulation and experimental results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-07-31 13:14:52.149