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The goal of neuromorphic engineering is to create electronic systems that model the behavior of biological neural systems. Neuromorphic systems can leverage a combination of analog and digital circuit design techniques to enable computational modeling, with orders of magnitude of reduction in size, weight, and power consumption compared to the traditional modeling approach based upon numerical integration. These benefits of neuromorphic modeling have the potential to facilitate neural modeling in resource-constrained research environments. Moreover, they will make it practical to use neural computation in the design of intelligent machines, including portable, battery-powered, and energy harvesting applications. Floating-gate transistor technology is a powerful tool for neuromorphic engineering because it allows dense implementation of synapses with nonvolatile storage of synaptic weights, cancellation of process mismatch, and reconfigurable system design. A novel neuromorphic hardware system, featuring compact and efficient channel-based model neurons and floating-gate transistor synapses, was developed. This system was used to model a variety of network topologies with up to 100 neurons. The networks were shown to possess computational capabilities such as spatio-temporal pattern generation and recognition, winner-take-all competition, bistable activity implementing a "volatile memory", and wavefront-based robotic path planning. Some canonical features of synaptic plasticity, such as potentiation of high frequency inputs and potentiation of correlated inputs in the presence of uncorrelated noise, were demonstrated. Preliminary results regarding formation of receptive fields were obtained. Several advances in enabling technologies, including methods for floating-gate transistor array programming, and the creation of a reconfigurable system for studying adaptation in floating-gate transistor circuits, were made.

La conception de circuit à très faible tension d'alimentation est un moyen depuis longtemps connu pour diminuer la consommation d'énergie des circuits pour un même service rendu [VITTOZ weak inversion]. La faible tension permet de gagner à la fois en courant de fuite [K ROY leakage] et surtout en courant dynamique qui reste la partie de l'énergie consommée la plus ardue a maîtriser. Elle s'accompagne d'un délai multiplié par plusieurs ordres de grandeur et une sensibilité accrue aux variations de paramètres des dispositifs. Cette variation étant plus grande dans les technologies récentes, la conception à très faible tension était jusqu'à récemment limitée aux nœuds technologiques en deçà de 40nm, mais des avancées récentes en technologie 32nm ont été publiés [TI ISSCC2011]. Un premier travail de thèse [ABOUZEID PhD], a permis de confirmer la faisabilité de la conception de circuit ULV. Plus précisément ont été démontrées : · une méthodologie de conception de cellules logiques en technologie 90nm, 65nm, 45nm et 40nm · une adaptation des flots automatiques d'implémentation et de vérification en 40nm · un précurseur de SRAM en CMOS65nm Sur cette base le présent travail de thèse consistera en l'élargissement de l'éventail du champ de conception ULV vers la gestion d'alimentation, la compensation des conditions environnementales et l'optimisation architecturale afin de préparer l'industrialisation de futures applications ULV. / IoT applications continue to push towards ultra-low-power constrained ASICs, creating severe challenges to achieve sufficient power efficiency in extreme Voltage and Temperature conditions. Thus, it is necessary to build closed-loop compensation systems that are autonomous to environmental conditions especially temperature at sub-threshold regime. Two major work are proposed: an adaptive techniques that allow to enhance the performance of designs that leverage aggressive voltage scaling. we fully exploits the FD-SOI 28nm technology dual gate capabilities to both attain optimal power efficiency points and compensate for gradual changes in overall device performance due to process, voltage, and temperature variations. Our proposed compensation Unit system is a fully-digital error-prediction solution providing a compromise between industry reliability requirements and manufacturing guard-band reduction with low-invasiveness and post-silicon tunability. Critical-Paths timing monitors are distributed across the processor and tuned to match the closest critical paths. A programmable workload emulator allows to adapt and take into account the processor tasks. Generated warning Flags due to V-T variations are analyzed based on an adjustable warning rate and body bias is adapted correspondingly. Based on the operation voltage, either fine or coarse body biasing can be activated for compensation. The second part of this thesis addresses on-chip temperature monitoring that plagues aggressively voltage scaled ASICs. We propose to closely monitor temperature fluctuations at low-voltage but also hot-spot detection at nominal and over-drive supply voltage conditions.