­^¤å´£­n¡G Two different topics associated with their respective applications are proposed in this thesis. The first topic is focused on the implementation of a 4-Kb 500MHz 4-T CMOS SRAM using low-Vthn bitline drivers and high-Vthp latches. The storage of data is realized by a pair of cross-coupled PMOS transistors, while the wordline is controlled by a pair of NMOS transistors. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. The second topic is the implementation of cascade address transition detector (ATD) design with high noise immunity. We employ a feedback loop to prevent interference of noise and false alarm signal to stabilize the generated CS (Chip Select) signal. Besides, we use one delay buffer to dynamically adjust the CS strobe.