In recent high-speed digital circuits, the simultaneous switching noise (SSN) or ground bounce noise (GBN) is induced due to the transient currents flowing between power and ground planes during the state transitions of the logic gates. In order to¡@analyze the effect of GBN on power delivery systems effectively and accurately, the impedance of power/ground is an important index to evaluate power delivery systems. In the operating frequency bandwidth, the power impedance must be less than the target impedance. The typical way to suppress the SSN is adding decoupling capacitors to create a low impedance path between power and ground planes. By using the admittance matrix method, we can evaluate the effect of decoupling capacitors mounted on PCB fast and accurately reducing the time needed from the empirical or try-and-error design cycle. In order to reduce the cost of decoupling capacitors, the genetic algorithm is employed to optimize the placement of decoupling capacitors to suppress the GBN. The decoupling capacitor are not effective in the GHz frequency range due to their inherent lead inductance. The electromagnetic bandgap(EBG) structure can produce a stopband to prevent the noise from disperseing at higher frequency. Combining decoupling capacitors with EBG structure to find the optimum placement for suppression of the SSN by using the genetic algorithm.