For the past four decades, Moore's law has been the most important benchmark in microelectronic circuits. Continuous improvement in lithographic technology has key enabler for growth in transistor density. In recent times, the wavelength of the light source has not kept its pace in scaling. Consequently, modern devices have feature sizes that are smaller than the wavelength of light source used currently in lithography. Printability in sub-wavelength lithography is one of the contemporary research issues. Some of the printability issues arise from optical defocus, lens aberration, wafer tilting, isotropic etching and resist thickness variation. Many of such sources lead to line width variation in today's layouts. In this work we propose to simulate such lithographic variation and estimate their impact on current devices and interconnects. We also propose to model such effects and aim to provide measures at the design level to mitigate these problems. Variations arising out of lithography process also impact yield and performance. We plan to study the impact of sub-wavelength lithography on yield and provide solutions for its measure, and directed pattern developement and testing.